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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-23 13:06:31 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-23 13:06:31 -0700 |
| commit | 242b3083eac817c927624db735ca3196223f97c0 (patch) | |
| tree | 0d15e8b6fc2a1d991edde2face6d637cfa589d50 | |
| parent | cee30deef5f48b97af961ecb6f7194eac14d891c (diff) | |
| download | yosys-242b3083eac817c927624db735ca3196223f97c0.tar.gz yosys-242b3083eac817c927624db735ca3196223f97c0.tar.bz2 yosys-242b3083eac817c927624db735ca3196223f97c0.zip | |
Cope with possibility that D could connect to Q on same cell
| -rw-r--r-- | passes/pmgen/xilinx_srl.pmg | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/pmgen/xilinx_srl.pmg b/passes/pmgen/xilinx_srl.pmg index fffff91e8..5d74b91bc 100644 --- a/passes/pmgen/xilinx_srl.pmg +++ b/passes/pmgen/xilinx_srl.pmg @@ -197,7 +197,7 @@ match next select !next->has_keep_attr() select !port(next, \D)[0].wire->get_bool_attribute(\keep) slice idx GetSize(port(next, \Q)) - select nusers(port(next, \Q)[idx]) == 3 + select nusers(port(next, \Q)[idx]) <= 3 index <IdString> next->type === chain.back().first->type index <SigBit> port(next, \Q)[idx] === port(chain.back().first, \D)[chain.back().second] index <SigBit> port(next, \Q)[idx] === port(shiftx, \A)[shiftx_width-1-GetSize(chain)] |