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| | * | | | write_xaiger to use scratchpad for stats; cleanup abc9Eddie Hung2019-12-302-190/+20
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| | * | | | Remove submod changesEddie Hung2019-12-302-201/+37
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| | * | | | Remove unusedEddie Hung2019-12-301-5/+0
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| | * | | | Do not offset FD* box timings due to -46ps TsuEddie Hung2019-12-301-12/+21
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| | * | | | Call "proc" if processes inside whiteboxesEddie Hung2019-12-301-1/+1
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| | * | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-3042-211/+1731
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| | * | | | | Add CHANGELOG entry, add abc9_{flop,keep} attr to README.mdEddie Hung2019-12-302-0/+7
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| | * | | | | Tidy up abc9_map.vEddie Hung2019-12-301-103/+103
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| | * | | | | Add "synth_xilinx -dff" option, cleanup abc9Eddie Hung2019-12-304-53/+120
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| | * | | | | GrammarEddie Hung2019-12-301-1/+1
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| | * | | | | Really fix it!Eddie Hung2019-12-271-10/+7
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| | * | | | | write_xaiger: fix arrival times for non boxesEddie Hung2019-12-271-18/+25
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| | * | | | | Disable clock domain partitioning in Yosys pass, let ABC do itEddie Hung2019-12-231-6/+22
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| | * | | | | write_xaiger to opt instead of just clean whiteboxesEddie Hung2019-12-231-1/+1
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| | * | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-201-24/+10
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| | * \ \ \ \ \ Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-2011-216/+339
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| | * | | | | | | Add RAM{32,64}M to abc9_map.vEddie Hung2019-12-191-0/+78
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| | * | | | | | | Split into $__ABC9_ASYNC[01], do not add cell->type to clkdomain_tEddie Hung2019-12-196-41/+60
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| | * | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-1947-161/+2030
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| | * | | | | | | | Bump ABC againEddie Hung2019-12-181-1/+1
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| | * | | | | | | | Remove &verify -sEddie Hung2019-12-171-1/+1
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| | * | | | | | | | Bump ABC for upstream fixEddie Hung2019-12-171-1/+1
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| | * | | | | | | | Use pool<> instead of std::set<> to preserver orderingEddie Hung2019-12-171-6/+6
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| | * | | | | | | | aiger frontend to user shorter, $-prefixed, namesEddie Hung2019-12-171-14/+14
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| | * | | | | | | | Cleanup xaiger, remove unnecessary complexity with inoutEddie Hung2019-12-172-84/+24
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| | * | | | | | | | read_xaiger to cope with optional '\n' after 'c'Eddie Hung2019-12-171-2/+2
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| | * | | | | | | | Do not sigmapEddie Hung2019-12-171-1/+1
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| | * | | | | | | | Revert "Use sigmap signal"Eddie Hung2019-12-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 42f990f3a6b7928841fa0e290fa2688925485907.
| | * | | | | | | | abc9 needs a clean afterwardsEddie Hung2019-12-161-2/+4
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| | * | | | | | | | Put $__ABC9_{FF_,ASYNC} into same clock domain as abc9_flopEddie Hung2019-12-161-5/+27
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| | * | | | | | | | Use sigmap signalEddie Hung2019-12-161-1/+1
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| | * | | | | | | | Skip $inout transformation if not a PIEddie Hung2019-12-161-3/+5
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| | * | | | | | | | Revert "write_xaiger: use sigmap bits more consistently"Eddie Hung2019-12-161-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 6c340112fee1bb8989cbd41923aaa627d77d5110.
| | * | | | | | | | write_xaiger: use sigmap bits more consistentlyEddie Hung2019-12-161-5/+4
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| | * | | | | | | | Name inputs/outputs of aiger 'i%d' and 'o%d'Eddie Hung2019-12-131-13/+6
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| | * | | | | | | | Remove 'clkpart' entry in CHANGELOGEddie Hung2019-12-121-1/+0
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| | * | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-1218-64/+238
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| | * | | | | | | | | abc9_map.v: fix Xilinx LUTRAMEddie Hung2019-12-121-6/+6
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| | * | | | | | | | | Fix commentEddie Hung2019-12-091-1/+1
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| | * | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-0619-971/+1773
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| | * | | | | | | | | | Call abc9 with "&write -n", and parse_xaiger() to copeEddie Hung2019-12-062-94/+87
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| | * | | | | | | | | | Remove creation of $abc9_control_wireEddie Hung2019-12-061-16/+6
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| | * | | | | | | | | | Do not connect undriven POs to 1'bxEddie Hung2019-12-061-8/+3
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| | * | | | | | | | | | Fix abc9 re-integration, remove abc9_control_wire, use cell->type asEddie Hung2019-12-061-39/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | as part of clock domain for mergeability class
| | * | | | | | | | | | Fix writing non-whole modules, including inouts and keepsEddie Hung2019-12-061-90/+81
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| | * | | | | | | | | | abc9 to use mergeability class to differentiate sync/asyncEddie Hung2019-12-061-12/+15
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| | * | | | | | | | | | write_xaiger to support part-selected modules againEddie Hung2019-12-051-11/+37
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| | * | | | | | | | | | abc9 to do clock partitioning againEddie Hung2019-12-051-37/+144
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| | * | | | | | | | | | Remove clkpartEddie Hung2019-12-053-313/+0
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| | * | | | | | | | | | Revert "Special abc9_clock wire to contain only clock signal"Eddie Hung2019-12-051-10/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 6a2eb5d8f9286b9574647c03e2bdc8b63fccbe4d.
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-08 18:55:40 +0000