Cleanup xaiger, remove unnecessary complexity with inout

2 files changed, 24 insertions, 84 deletions

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 8db166fc2..af52daa0c 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -264,9 +264,22 @@ struct XAigerWriter
 							bit_users[bit].insert(cell->name);
 					}
 
-					if (port_wire->port_output)
-						for (auto bit : sigmap(conn.second))
+					if (port_wire->port_output) {
+						int arrival = 0;
+						auto it = port_wire->attributes.find("\\abc9_arrival");
+						if (it != port_wire->attributes.end()) {
+							if (it->second.flags != 0)
+								log_error("Attribute 'abc9_arrival' on port '%s' of module '%s' is not an integer.\n", log_id(port_wire), log_id(cell->type));
+							arrival = it->second.as_int();
+						}
+
+						for (auto bit : sigmap(conn.second)) {
 							bit_drivers[bit].insert(cell->name);
+							if (arrival)
+								arrival_times[bit] = arrival;
+						}
+					}
+
 				}
 
 				if (inst_module->attributes.count("\\abc9_flop"))
@@ -291,35 +304,12 @@ struct XAigerWriter
 							SigBit I = sigmap(b);
 							if (I != b)
 								alias_map[b] = I;
-							output_bits.insert(b);
-
-							if (!cell_known)
-								inout_bits.insert(b);
-						}
-					}
-				}
-				if (is_output) {
-					int arrival = 0;
-					if (port_wire) {
-						auto it = port_wire->attributes.find("\\abc9_arrival");
-						if (it != port_wire->attributes.end()) {
-							if (it->second.flags != 0)
-								log_error("Attribute 'abc9_arrival' on port '%s' of module '%s' is not an integer.\n", log_id(port_wire), log_id(cell->type));
-							arrival = it->second.as_int();
+							if (holes_mode)
+								output_bits.insert(b);
+							else
+								external_bits.insert(b);
 						}
 					}
-
-					for (auto b : c.second) {
-						Wire *w = b.wire;
-						if (!w) continue;
-						SigBit O = sigmap(b);
-						if (O != b)
-							alias_map[O] = b;
-						input_bits.insert(b);
-
-						if (arrival)
-							arrival_times[b] = arrival;
-					}
 				}
 			}
 
@@ -471,7 +461,7 @@ struct XAigerWriter
 							SigBit O = sigmap(b);
 							if (O != b)
 								alias_map[O] = b;
-							input_bits.erase(b);
+							input_bits.erase(O);
 							undriven_bits.erase(O);
 						}
 					}
@@ -542,37 +532,6 @@ struct XAigerWriter
 				undriven_bits.erase(bit);
 			}
 
-		// For inout ports, or keep-ed wires, that end up as both a PI and a
-		// PO, then create a new PO with an $inout.out suffix that is driven
-		// by the existing inout, and inherit its drivers
-		for (auto bit : inout_bits) {
-			if (!input_bits.count(bit))
-				continue;
-			RTLIL::Wire *wire = bit.wire;
-			RTLIL::IdString wire_name = stringf("$%s$inout.out", wire->name.c_str());
-			RTLIL::Wire *new_wire = module->wire(wire_name);
-			if (!new_wire)
-				new_wire = module->addWire(wire_name, GetSize(wire));
-			SigBit new_bit(new_wire, bit.offset);
-			module->connect(new_bit, bit);
-			if (not_map.count(bit)) {
-				auto a = not_map.at(bit);
-				not_map[new_bit] = a;
-			}
-			else if (and_map.count(bit)) {
-				auto a = and_map.at(bit);
-				and_map[new_bit] = a;
-			}
-			else if (alias_map.count(bit)) {
-				auto a = alias_map.at(bit);
-				alias_map[new_bit] = a;
-			}
-			else
-				alias_map[new_bit] = bit;
-			output_bits.erase(bit);
-			output_bits.insert(new_bit);
-		}
-
 		if (holes_mode) {
 			struct sort_by_port_id {
 				bool operator()(const RTLIL::SigBit& a, const RTLIL::SigBit& b) const {
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index abc2f4144..613723966 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -887,16 +887,7 @@ void AigerReader::post_process()
 					// simply connect the latter to the former
 					RTLIL::Wire* existing = module->wire(escaped_s);
 					if (!existing) {
-						if (escaped_s.ends_with("$inout.out")) {
-							wire->port_output = false;
-							RTLIL::Wire *in_wire = module->wire(escaped_s.substr(1, escaped_s.size()-11));
-							log_assert(in_wire);
-							log_assert(in_wire->port_input && !in_wire->port_output);
-							in_wire->port_output = true;
-							module->connect(in_wire, wire);
-						}
-						else
-							module->rename(wire, escaped_s);
+						module->rename(wire, escaped_s);
 					}
 					else {
 						wire->port_output = false;
@@ -908,19 +899,9 @@ void AigerReader::post_process()
 					std::string indexed_name = stringf("%s[%d]", escaped_s.c_str(), index);
 					RTLIL::Wire* existing = module->wire(indexed_name);
 					if (!existing) {
-						if (escaped_s.ends_with("$inout.out")) {
-							wire->port_output = false;
-							RTLIL::Wire *in_wire = module->wire(stringf("%s[%d]", escaped_s.substr(1, escaped_s.size()-11).c_str(), index));
-							log_assert(in_wire);
-							log_assert(in_wire->port_input && !in_wire->port_output);
-							in_wire->port_output = true;
-							module->connect(in_wire, wire);
-						}
-						else {
-							module->rename(wire, indexed_name);
-							if (wideports)
-								wideports_cache[escaped_s] = std::max(wideports_cache[escaped_s], index);
-						}
+						module->rename(wire, indexed_name);
+						if (wideports)
+							wideports_cache[escaped_s] = std::max(wideports_cache[escaped_s], index);
 					}
 					else {
 						module->connect(wire, existing);