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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-27 15:18:55 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-27 15:18:55 -0800 |
| commit | dd503a5f3f50ec9762aa7301b5e0c5112aff1866 (patch) | |
| tree | e2fa76a9d881e3fbe947ecd41f56e527974a3157 | |
| parent | 49881b4468bbd02ac141495dd3b30c9739eb5072 (diff) | |
| download | yosys-dd503a5f3f50ec9762aa7301b5e0c5112aff1866.tar.gz yosys-dd503a5f3f50ec9762aa7301b5e0c5112aff1866.tar.bz2 yosys-dd503a5f3f50ec9762aa7301b5e0c5112aff1866.zip | |
Really fix it!
| -rw-r--r-- | backends/aiger/xaiger.cc | 17 |
1 files changed, 7 insertions, 10 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index e03f95eaa..80077c10a 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -255,32 +255,29 @@ struct XAigerWriter for (const auto &conn : cell->connections()) { auto port_wire = inst_module->wire(conn.first); - int arrival = 0; if (port_wire->port_output) { + int arrival = 0; auto it = port_wire->attributes.find("\\abc9_arrival"); if (it != port_wire->attributes.end()) { if (it->second.flags != 0) log_error("Attribute 'abc9_arrival' on port '%s' of module '%s' is not an integer.\n", log_id(port_wire), log_id(cell->type)); arrival = it->second.as_int(); } + if (arrival) + for (auto bit : sigmap(conn.second)) + arrival_times[bit] = arrival; } if (abc9_box) { - if (port_wire->port_input) { - // Ignore inout for the sake of topographical ordering - if (port_wire->port_output) continue; + // Ignore inout for the sake of topographical ordering + if (port_wire->port_input && !port_wire->port_output) for (auto bit : sigmap(conn.second)) bit_users[bit].insert(cell->name); - } if (port_wire->port_output) - for (auto bit : sigmap(conn.second)) { + for (auto bit : sigmap(conn.second)) bit_drivers[bit].insert(cell->name); - if (arrival) - arrival_times[bit] = arrival; - } } - } if (abc9_box) { |