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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-30 14:33:05 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-30 14:33:05 -0800 |
| commit | 3cbbae251fc4a4b10abe21fde9c7316bb940a957 (patch) | |
| tree | 38689c94ed84e06ffc8bf3fca3db2dbb43b67da0 | |
| parent | 405e974fe51f4ede0b374ddddc398a26e04b0265 (diff) | |
| download | yosys-3cbbae251fc4a4b10abe21fde9c7316bb940a957.tar.gz yosys-3cbbae251fc4a4b10abe21fde9c7316bb940a957.tar.bz2 yosys-3cbbae251fc4a4b10abe21fde9c7316bb940a957.zip | |
Call "proc" if processes inside whiteboxes
| -rw-r--r-- | backends/aiger/xaiger.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index bfdae7160..8e8f29457 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -706,7 +706,7 @@ struct XAigerWriter IdString derived_name = orig_box_module->derive(module->design, cell->parameters); RTLIL::Module* box_module = module->design->module(derived_name); if (box_module->has_processes()) - log_error("ABC9 box '%s' contains processes!\n", box_module->name.c_str()); + Pass::call_on_module(module->design, box_module, "proc"); int box_inputs = 0, box_outputs = 0; auto r = cell_cache.insert(std::make_pair(derived_name, nullptr)); |