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* abc9: not enough to techmap_fail on (* init=1 *), hide them using $__Eddie Hung2020-05-144-12/+48
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* abc9: test to use box file instead of autoEddie Hung2020-05-143-2/+5
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* abc9: restore selected_modules()Eddie Hung2020-05-141-1/+1
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* synth_*: no need to explicitly read +/abc9_model.vEddie Hung2020-05-144-4/+3
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* Revert "Merge pull request #1917 from YosysHQ/eddie/abc9_delay_check"Eddie Hung2020-05-141-4/+0
| | | | | This reverts commit 759283fa65b1195ebe3a5bc6890ec622febca0eb, reversing changes made to f41c7ccfff4bf104c646ca4b85e079a0f91c9151.
* abc9: add flop boxes to basic $_DFF_P_ and $_DFF_N_ tooEddie Hung2020-05-147-24/+88
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* kernel: TimingInfo to clamp -ve setup/edge-sensitive delays to zeroEddie Hung2020-05-141-10/+6
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* abc9_ops: -prep_dff_map to error if async flop foundEddie Hung2020-05-142-9/+7
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* Uncomment negative setup times; clamp to zero for connectivityEddie Hung2020-05-141-13/+29
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* abc9: remove redundant wbflipEddie Hung2020-05-141-1/+0
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* xaiger: always sort input/output bits by port idEddie Hung2020-05-141-12/+10
| | | | redundant for normal design, but necessary for holes
* abc9: generate $abc9_holes design instead of <name>$holesEddie Hung2020-05-143-18/+28
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* abc9_ops: more robustEddie Hung2020-05-141-8/+14
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* abc9: suppress warnings when no compatible + used flop boxes formedEddie Hung2020-05-143-38/+66
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* xilinx: update abc9_dff testsEddie Hung2020-05-141-18/+45
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* xilinx: remove no-longer-relevant testEddie Hung2020-05-141-91/+0
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* aiger/xaiger: use odd for negedge clk, even for posedgeEddie Hung2020-05-142-10/+13
| | | | Since abc9 doesn't like negative mergeability values
* abc9: cleanupEddie Hung2020-05-141-7/+11
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* Revert "ecp5: replace ecp5_ffinit with techmap rules + dff2dffs -match-init"Eddie Hung2020-05-143-220/+64
| | | | This reverts commit 8c702b6cc0221a00021a3e4661c883bb591c924b.
* abc9_ops: -prep_dff_map to check $_DFF_[NP]_.Q drives module outputEddie Hung2020-05-141-1/+5
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* abc9_ops: do away with '$abc9_cells' selectionEddie Hung2020-05-142-40/+30
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* abc9_ops: use new 'design -delete' and 'select -unset'Eddie Hung2020-05-142-16/+7
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* ecp5: (* abc9_flop *) gated behind YOSYSEddie Hung2020-05-141-0/+2
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* submod: revert accidental changeEddie Hung2020-05-141-1/+1
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* Revert "Merge branch 'eddie/kernel_makeblackbox' into eddie/abc9_auto_dff"Eddie Hung2020-05-141-1/+0
| | | | | This reverts commit e08497c7c9d8a6f7a3eccddf2149c45d9ecff207, reversing changes made to e366fd55122236a21c6daee6765724add840a1f9.
* xaiger: update help textEddie Hung2020-05-141-4/+4
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* ecp5: add synth_ecp5 -dff to work with -abc9Eddie Hung2020-05-142-12/+47
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* abc9_ops: -prep_dff_map to warn if no specify cellsEddie Hung2020-05-141-7/+12
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* ice40: synth_ice40 cleanupEddie Hung2020-05-141-13/+3
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* ecp5: replace ecp5_ffinit with techmap rules + dff2dffs -match-initEddie Hung2020-05-143-64/+220
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* kernel: Module::makeblackbox() to clear connections + delete wires lastEddie Hung2020-05-141-0/+1
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* ice40: add synth_ice40 -dff option, support with -abc9Eddie Hung2020-05-142-8/+41
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* ice40: split out cells_map.v into ff_map.vEddie Hung2020-05-143-31/+29
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* abc9_ops: -prep_dff_map to cope with plain $_DFF_[NP]_ flopsEddie Hung2020-05-141-12/+39
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* synth_xilinx: rename dff_mode -> dffEddie Hung2020-05-141-8/+10
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* xaiger: do not treat (* init=1'bx *) as 1'b0Eddie Hung2020-05-141-1/+1
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* abc9: cleanupEddie Hung2020-05-141-4/+1
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* abc9_ops: do not use (* abc9_init *)Eddie Hung2020-05-141-16/+31
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* aiger: -xaiger to parse initial state back into (* init *) on Q wireEddie Hung2020-05-141-1/+2
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* xaiger: when -dff use (* init *) for initial stateEddie Hung2020-05-141-3/+15
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* abc9_ops: add 'dff' label for auto handling of (* abc9_flop *) boxesEddie Hung2020-05-149-635/+398
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* abc9: fix behaviour and help for -box optionEddie Hung2020-05-141-3/+7
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* aiger: -xaiger to read $_DFF_[NP]_ back with new clocks createdEddie Hung2020-05-142-3/+24
| | | | according to mergeability class, and init state as cell attr
* xaiger: output $_DFF_[NP]_ with mergeability if -dff optionEddie Hung2020-05-141-42/+44
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* Merge pull request #2045 from YosysHQ/eddie/fix2042Eddie Hung2020-05-146-1/+107
|\ | | | | verilog: error if no direction given for task arguments, default to input in SV mode
| * test: add another testcase as per @nakengelhardtEddie Hung2020-05-141-0/+25
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| * verilog: default to input in sv mode if task/func has no dir ...Eddie Hung2020-05-131-2/+10
| | | | | | | | otherwise error
| * tests: update/extend task argument testsEddie Hung2020-05-132-2/+35
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| * verilog: error out when non-ANSI task/func argumentsEddie Hung2020-05-111-1/+5
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| * tests: add #2042 testcaseEddie Hung2020-05-111-0/+12
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