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| author | Eddie Hung <eddie@fpgeh.com> | 2020-04-13 13:10:57 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-14 10:33:56 -0700 |
| commit | 77f3abcdc30e21b4359c2b07c20b63bdac5993bf (patch) | |
| tree | 130efc7c42657e53cb5f09f1a9dfa67decf90a33 | |
| parent | 95763c8d18eec49de3acff5d38a82f54cc25cb1b (diff) | |
| download | yosys-77f3abcdc30e21b4359c2b07c20b63bdac5993bf.tar.gz yosys-77f3abcdc30e21b4359c2b07c20b63bdac5993bf.tar.bz2 yosys-77f3abcdc30e21b4359c2b07c20b63bdac5993bf.zip | |
xaiger: when -dff use (* init *) for initial state
| -rw-r--r-- | backends/aiger/xaiger.cc | 18 |
1 files changed, 15 insertions, 3 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 2e2ca7018..5d15df310 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -79,6 +79,7 @@ struct XAigerWriter Module *module; SigMap sigmap; + dict<SigBit, State> init_map; pool<SigBit> input_bits, output_bits; dict<SigBit, SigBit> not_map, alias_map; dict<SigBit, pair<SigBit, SigBit>> and_map; @@ -157,7 +158,8 @@ struct XAigerWriter if (wire->get_bool_attribute(ID::keep)) sigmap.add(wire); - for (auto wire : module->wires()) + for (auto wire : module->wires()) { + auto it = wire->attributes.find(ID::init); for (int i = 0; i < GetSize(wire); i++) { SigBit wirebit(wire, i); @@ -184,7 +186,17 @@ struct XAigerWriter alias_map[wirebit] = bit; output_bits.insert(wirebit); } + + if (it != wire->attributes.end()) { + auto s = it->second[i]; + if (s != State::Sx) { + auto r = init_map.insert(std::make_pair(bit, it->second[i])); + if (!r.second && r.first->second != it->second[i]) + log_error("Bit '%s' has a conflicting (* init *) value.\n", log_signal(bit)); + } + } } + } TimingInfo timing; @@ -632,8 +644,8 @@ struct XAigerWriter write_r_buffer(mergeability); else log_abort(); - Const init = cell->attributes.at(ID::abc9_init); - log_assert(GetSize(init) == 1); + SigBit Q = sigmap(cell->getPort(ID::Q)); + State init = init_map.at(Q, State::Sx); if (init == State::S1) write_s_buffer(1); else if (init == State::S0) |