diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2020-05-14 08:36:36 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-14 08:36:36 -0700 |
| commit | 56a5b1d2daf1b244990d81f32183034071ebd185 (patch) | |
| tree | 675dae9473a9e2d5ba62056d15b0887417cc89cf | |
| parent | 237962debd9fcb7e9fb45f53bc8a53f0c34d9888 (diff) | |
| download | yosys-56a5b1d2daf1b244990d81f32183034071ebd185.tar.gz yosys-56a5b1d2daf1b244990d81f32183034071ebd185.tar.bz2 yosys-56a5b1d2daf1b244990d81f32183034071ebd185.zip | |
test: add another testcase as per @nakengelhardt
| -rw-r--r-- | tests/verilog/bug2042-sv.ys | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/tests/verilog/bug2042-sv.ys b/tests/verilog/bug2042-sv.ys index 9a0d419c8..e815d7fc5 100644 --- a/tests/verilog/bug2042-sv.ys +++ b/tests/verilog/bug2042-sv.ys @@ -21,6 +21,31 @@ sat -verify -prove-asserts design -reset +read_verilog -sv <<EOT +module Task_Test_Top +( +input a, +output b, c +); + + task SomeTaskName(x, output y, z); + y = ~x; + z = x; + endtask + + always @* + SomeTaskName(a, b, c); + + assert property (b == ~a); + assert property (c == a); + +endmodule +EOT +proc +sat -verify -prove-asserts + + +design -reset logger -expect error "syntax error, unexpected TOK_ENDTASK, expecting ';'" 1 read_verilog -sv <<EOT module Task_Test_Top |