| Commit message (Expand) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| * | proc_prune: Make assign removal and promotion per-bit, remember promoted bits. | Marcelina Kościelnicka | 2021-08-14 | 2 | -40/+47 | |
| * | Bump version | github-actions[bot] | 2021-08-14 | 1 | -1/+1 | |
| * | Generate an RTLIL representation of bind constructs | Rupert Swarbrick | 2021-08-13 | 11 | -3/+312 | |
| * | Add opt_mem_widen pass. | Marcelina Kościelnicka | 2021-08-14 | 4 | -0/+146 | |
| * | memory_share: Add -nosat and -nowiden options. | Marcelina Kościelnicka | 2021-08-14 | 11 | -11/+269 | |
| * | memory_dff: Recognize soft transparency logic. | Marcelina Kościelnicka | 2021-08-13 | 4 | -7/+1355 | |
| * | Add new opt_mem_priority pass. | Marcelina Kościelnicka | 2021-08-13 | 4 | -2/+319 | |
| * | Merge pull request #2932 from YosysHQ/mwk/logger-check-expected | Miodrag Milanović | 2021-08-13 | 2 | -5/+14 | |
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| | * | logger: Add -check-expected subcommand. | Marcelina Kościelnicka | 2021-08-12 | 2 | -5/+14 | |
| * | | sv: improve support for wire and var with user-defined types | Brett Witherspoon | 2021-08-12 | 3 | -11/+152 | |
| * | | Bump version | github-actions[bot] | 2021-08-13 | 1 | -1/+1 | |
| * | | memory_share: Pass addresses through sigmap_xmux everywhere. | Marcelina Kościelnicka | 2021-08-13 | 1 | -20/+25 | |
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| * | Bump version | github-actions[bot] | 2021-08-12 | 1 | -1/+1 | |
| * | test/arch/{ecp5,ice40}/memories.ys: Use read_verilog -defer. | Marcelina Kościelnicka | 2021-08-11 | 2 | -78/+156 | |
| * | memory_dff: Recognize read ports with reset / initial value. | Marcelina Kościelnicka | 2021-08-11 | 4 | -8/+55 | |
| * | proc_memwr: Use the v2 memwr cell. | Marcelina Kościelnicka | 2021-08-11 | 3 | -14/+24 | |
| * | Add v2 memory cells. | Marcelina Kościelnicka | 2021-08-11 | 22 | -206/+631 | |
| * | Bump version | github-actions[bot] | 2021-08-11 | 1 | -1/+1 | |
| * | kernel/mem: Introduce transparency masks. | Marcelina Kościelnicka | 2021-08-11 | 8 | -118/+408 | |
| * | Allow optional comma after last entry in enum | Michael Singer | 2021-08-09 | 1 | -11/+12 | |
| * | Bump version | github-actions[bot] | 2021-08-10 | 1 | -1/+1 | |
| * | Refactor common parts of SAT-using optimizations into a helper. | Marcelina Kościelnicka | 2021-08-09 | 7 | -153/+224 | |
| * | Bump version | github-actions[bot] | 2021-08-08 | 1 | -1/+1 | |
| * | opt_merge: Use FfInitVals. | Marcelina Kościelnicka | 2021-08-08 | 3 | -28/+51 | |
| * | Bump version | github-actions[bot] | 2021-08-07 | 1 | -1/+1 | |
| * | verilog: Support tri/triand/trior wire types. | Marcelina Kościelnicka | 2021-08-06 | 1 | -0/+3 | |
| * | Bump version | github-actions[bot] | 2021-08-05 | 1 | -1/+1 | |
| * | memory_share: Don't skip ports with EN wired to input for SAT sharing. | Marcelina Kościelnicka | 2021-08-04 | 1 | -3/+1 | |
| * | Bump version | github-actions[bot] | 2021-08-04 | 1 | -1/+1 | |
| * | memory_bram: Move init data swizzling before other swizzling. | Marcelina Kościelnicka | 2021-08-03 | 1 | -18/+18 | |
| * | Bump version | github-actions[bot] | 2021-08-03 | 1 | -1/+1 | |
| * | Require latest verific | Miodrag Milanovic | 2021-08-02 | 1 | -1/+1 | |
| * | Bump version | github-actions[bot] | 2021-08-02 | 1 | -1/+1 | |
| * | backend/verilog: Add alternate mode for transparent read port output. | Marcelina Kościelnicka | 2021-08-01 | 1 | -1/+71 | |
| * | memory_bram: Some refactoring | Marcelina Kościelnicka | 2021-08-01 | 1 | -196/+174 | |
| * | Bump version | github-actions[bot] | 2021-07-31 | 1 | -1/+1 | |
| * | Update version.yml | Miodrag Milanović | 2021-07-30 | 1 | -2/+5 | |
| * | Fixes xc7 BRAM36s | Maciej Dudek | 2021-07-30 | 1 | -4/+6 | |
| * | proc_rmdead: use explicit pattern set when there are no wildcards | Zachary Snow | 2021-07-29 | 4 | -2/+386 | |
| * | genrtlil: add width detection for AST_PREFIX nodes | Zachary Snow | 2021-07-29 | 2 | -0/+26 | |
| * | Bump version | github-actions[bot] | 2021-07-30 | 1 | -1/+1 | |
| * | opt_lut: Allow more than one -dlogic per cell type. | Marcelina Kościelnicka | 2021-07-29 | 3 | -24/+55 | |
| * | verilog: save and restore overwritten macro arguments | Zachary Snow | 2021-07-28 | 4 | -4/+54 | |
| * | Bump version | github-actions[bot] | 2021-07-29 | 1 | -1/+1 | |
| * | verilog: Emit $meminit_v2 cell. | Marcelina Kościelnicka | 2021-07-28 | 5 | -55/+87 | |
| * | backends/verilog: Support meminit with mask. | Marcelina Kościelnicka | 2021-07-28 | 1 | -3/+18 | |
| * | memory: Introduce $meminit_v2 cell, with EN input. | Marcelina Kościelnicka | 2021-07-28 | 10 | -13/+86 | |
| * | Bump version | github-actions[bot] | 2021-07-28 | 1 | -1/+1 | |
| * | proc: Run opt_expr at the end | Marcelina Kościelnicka | 2021-07-27 | 1 | -0/+11 | |
| * | opt_expr: Propagate constants to port connections. | Marcelina Kościelnicka | 2021-07-27 | 3 | -3/+37 | |
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index : iCE40/yosys | |
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