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| author | Maciej Dudek <mdudek@antmicro.com> | 2021-07-29 21:10:02 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-07-30 16:17:22 +0200 |
| commit | cfddef5d7d265d2260aad2d6ea8595f8b660eb6a (patch) | |
| tree | 09b9f1983c37497f7d96060f91990ad062e7934a | |
| parent | c016f6a4236fb970196f35c2afb0f2c7c237a77f (diff) | |
| download | yosys-cfddef5d7d265d2260aad2d6ea8595f8b660eb6a.tar.gz yosys-cfddef5d7d265d2260aad2d6ea8595f8b660eb6a.tar.bz2 yosys-cfddef5d7d265d2260aad2d6ea8595f8b660eb6a.zip | |
Fixes xc7 BRAM36s
UG473 from Xilinx states that 15 bit should always be set if RAMB isn't in cascade mode.
Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
| -rw-r--r-- | techlibs/xilinx/xc7_brams_map.v | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/techlibs/xilinx/xc7_brams_map.v b/techlibs/xilinx/xc7_brams_map.v index 2b6ad0da6..982a5a07e 100644 --- a/techlibs/xilinx/xc7_brams_map.v +++ b/techlibs/xilinx/xc7_brams_map.v @@ -16,8 +16,9 @@ module \$__XILINX_RAMB36_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, input [71:0] B1DATA; input [7:0] B1EN; - wire [15:0] A1ADDR_16 = {A1ADDR, 6'b0}; - wire [15:0] B1ADDR_16 = {B1ADDR, 6'b0}; + // Set highest address bit to 1, as stated in UG473 (v1.14) July 3, 2019 + wire [15:0] A1ADDR_16 = {1'b1, A1ADDR, 6'b0}; + wire [15:0] B1ADDR_16 = {1'b1, B1ADDR, 6'b0}; wire [7:0] DIP, DOP; wire [63:0] DI, DO; @@ -153,8 +154,9 @@ module \$__XILINX_RAMB36_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, input [CFG_DBITS-1:0] B1DATA; input [CFG_ENABLE_B-1:0] B1EN; - wire [15:0] A1ADDR_16 = A1ADDR << (15 - CFG_ABITS); - wire [15:0] B1ADDR_16 = B1ADDR << (15 - CFG_ABITS); + // Set highest address bit to 1, as stated in UG473 (v1.14) July 3, 2019 + wire [15:0] A1ADDR_16 = {1'b1, A1ADDR} << (15 - CFG_ABITS); + wire [15:0] B1ADDR_16 = {1'b1, B1ADDR} << (15 - CFG_ABITS); wire [7:0] B1EN_8 = B1EN; wire [3:0] DIP, DOP; |