diff options
| author | Marcelina Kościelnicka <mwk@0x04.net> | 2021-08-06 20:49:41 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-08-06 21:35:43 +0200 |
| commit | 52cbf1bea52b05c3fa57712ce201369c92400008 (patch) | |
| tree | d2f5cb82a4528a4e36f0e6ec9c9ea97ac74cd4a8 | |
| parent | 2e421feb0ea526468493ab008f3c72beb12c2bc6 (diff) | |
| download | yosys-52cbf1bea52b05c3fa57712ce201369c92400008.tar.gz yosys-52cbf1bea52b05c3fa57712ce201369c92400008.tar.bz2 yosys-52cbf1bea52b05c3fa57712ce201369c92400008.zip | |
verilog: Support tri/triand/trior wire types.
These are, by the standard, just aliases for wire/wand/wor.
Fixes #2918.
| -rw-r--r-- | frontends/verilog/verilog_lexer.l | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index 54fb65240..0306f5494 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -277,8 +277,11 @@ static bool isUserType(std::string &s) "output" { return TOK_OUTPUT; } "inout" { return TOK_INOUT; } "wire" { return TOK_WIRE; } +"tri" { return TOK_WIRE; } "wor" { return TOK_WOR; } +"trior" { return TOK_WOR; } "wand" { return TOK_WAND; } +"triand" { return TOK_WAND; } "reg" { return TOK_REG; } "integer" { return TOK_INTEGER; } "signed" { return TOK_SIGNED; } |