memory_dff: Recognize read ports with reset / initial value.

4 files changed, 55 insertions, 8 deletions

diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc
index e6b4b2400..8ad131c7c 100644
--- a/passes/memory/memory_dff.cc
+++ b/passes/memory/memory_dff.cc
@@ -60,11 +60,6 @@ struct MemoryDffWorker
 			log("output FF has both set and reset, not supported.\n");
 			return;
 		}
-		if (ff.has_srst || ff.has_arst || !ff.val_init.is_fully_undef()) {
-			// TODO: not supported yet
-			log("output FF has reset and/or init value, not supported yet.\n");
-			return;
-		}
 		merger.remove_output_ff(bits);
 		if (ff.has_en && !ff.pol_en)
 			ff.sig_en = module->LogicNot(NEW_ID, ff.sig_en);
@@ -79,7 +74,6 @@ struct MemoryDffWorker
 			port.en = ff.sig_en;
 		else
 			port.en = State::S1;
-#if 0
 		if (ff.has_arst) {
 			port.arst = ff.sig_arst;
 			port.arst_value = ff.val_arst;
@@ -94,7 +88,6 @@ struct MemoryDffWorker
 			port.srst = State::S0;
 		}
 		port.init_value = ff.val_init;
-#endif
 		port.data = ff.sig_q;
 		mem.emit();
 		log("merged output FF to cell.\n");
diff --git a/tests/memories/read_arst.v b/tests/memories/read_arst.v
new file mode 100644
index 000000000..6100cc4a7
--- /dev/null
+++ b/tests/memories/read_arst.v
@@ -0,0 +1,27 @@
+// expect-wr-ports 1
+// expect-rd-ports 1
+// expect-rd-clk \clk
+// expect-rd-en \re
+// expect-rd-arst-sig \reset
+// expect-rd-arst-val 8'01011010
+// expect-rd-init-val 8'00111100
+
+module top(input clk, input we, re, reset, input [7:0] addr, wdata, output reg [7:0] rdata);
+
+reg [7:0] bram[0:255];
+initial rdata = 8'h3c;
+
+always @(posedge clk) begin
+	if (we)
+		bram[addr] <= wdata;
+end
+
+always @(posedge clk, posedge reset) begin
+	if (reset)
+		rdata <= 8'h5a;
+	else if (re)
+		rdata <= bram[addr];
+end
+
+endmodule
+
diff --git a/tests/memories/read_two_mux.v b/tests/memories/read_two_mux.v
index 4f2e7e1cd..8b609c552 100644
--- a/tests/memories/read_two_mux.v
+++ b/tests/memories/read_two_mux.v
@@ -1,6 +1,9 @@
 // expect-wr-ports 1
 // expect-rd-ports 1
-// expect-no-rd-clk
+// expect-rd-clk \clk
+// expect-rd-en \re
+// expect-rd-srst-sig \reset
+// expect-rd-srst-val 8'00000000
 
 module top(input clk, input we, re, reset, input [7:0] addr, wdata, output reg [7:0] rdata);
 
diff --git a/tests/memories/run-test.sh b/tests/memories/run-test.sh
index cded3eb40..49922e3da 100755
--- a/tests/memories/run-test.sh
+++ b/tests/memories/run-test.sh
@@ -31,6 +31,30 @@ for f in `egrep -l 'expect-(wr-ports|rd-ports|rd-clk)' *.v`; do
 		grep -q "connect \\\\RD_CLK \\$(gawk '/expect-rd-clk/ { print $3; }' $f)\$" ${f%.v}.dmp ||
 				{ echo " ERROR: Unexpected read clock."; false; }
 	fi
+	if grep -q expect-rd-en $f; then
+		grep -q "connect \\\\RD_EN \\$(gawk '/expect-rd-en/ { print $3; }' $f)\$" ${f%.v}.dmp ||
+				{ echo " ERROR: Unexpected read enable."; false; }
+	fi
+	if grep -q expect-rd-srst-sig $f; then
+		grep -q "connect \\\\RD_SRST \\$(gawk '/expect-rd-srst-sig/ { print $3; }' $f)\$" ${f%.v}.dmp ||
+				{ echo " ERROR: Unexpected read sync reset."; false; }
+	fi
+	if grep -q expect-rd-srst-val $f; then
+		grep -q "parameter \\\\RD_SRST_VALUE $(gawk '/expect-rd-srst-val/ { print $3; }' $f)\$" ${f%.v}.dmp ||
+				{ echo " ERROR: Unexpected read sync reset value."; false; }
+	fi
+	if grep -q expect-rd-arst-sig $f; then
+		grep -q "connect \\\\RD_ARST \\$(gawk '/expect-rd-arst-sig/ { print $3; }' $f)\$" ${f%.v}.dmp ||
+				{ echo " ERROR: Unexpected read async reset."; false; }
+	fi
+	if grep -q expect-rd-arst-val $f; then
+		grep -q "parameter \\\\RD_ARST_VALUE $(gawk '/expect-rd-arst-val/ { print $3; }' $f)\$" ${f%.v}.dmp ||
+				{ echo " ERROR: Unexpected read async reset value."; false; }
+	fi
+	if grep -q expect-rd-init-val $f; then
+		grep -q "parameter \\\\RD_INIT_VALUE $(gawk '/expect-rd-init-val/ { print $3; }' $f)\$" ${f%.v}.dmp ||
+				{ echo " ERROR: Unexpected read init value."; false; }
+	fi
 	if grep -q expect-no-rd-clk $f; then
 		grep -q "connect \\\\RD_CLK 1'x\$" ${f%.v}.dmp ||
 				{ echo " ERROR: Expected no read clock."; false; }