| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Update doc for synth_xilinx | Eddie Hung | 2019-04-10 | 1 | -7/+8 |
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| * | Merge branch 'xaig' into xc7mux | Eddie Hung | 2019-04-10 | 1 | -24/+21 |
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| | * | parse_aiger() to rename all $lut cells after "clean" | Eddie Hung | 2019-04-10 | 1 | -24/+21 |
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| * | | ff_map.v after abc | Eddie Hung | 2019-04-10 | 1 | -5/+5 |
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| * | | Tidy up | Eddie Hung | 2019-04-10 | 1 | -1/+1 |
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| * | | Move map_cells to before map_luts | Eddie Hung | 2019-04-10 | 1 | -11/+12 |
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| * | | WIP for $shiftx to wide mux | Eddie Hung | 2019-04-10 | 1 | -1/+63 |
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| * | | Update LUT delays | Eddie Hung | 2019-04-10 | 1 | -11/+8 |
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| * | | Add cells.lut to techlibs/xilinx/ | Eddie Hung | 2019-04-09 | 2 | -0/+16 |
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| * | | synth_xilinx to call abc with -lut +/xilinx/cells.lut | Eddie Hung | 2019-04-09 | 1 | -2/+2 |
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| * | | Add delays to cells.box | Eddie Hung | 2019-04-09 | 1 | -4/+12 |
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| * | | Add "-lut <file>" support to abc9 | Eddie Hung | 2019-04-09 | 1 | -13/+31 |
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| * | | synth_xilinx with abc9 to use -box | Eddie Hung | 2019-04-09 | 1 | -1/+4 |
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| * | | Add techlibs/xilinx/cells.box | Eddie Hung | 2019-04-09 | 2 | -0/+6 |
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| * | | Add "-box" option to abc9 | Eddie Hung | 2019-04-09 | 1 | -7/+22 |
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| * | | Add 'setundef -zero' call prior to aigmap in abc9 | Eddie Hung | 2019-04-09 | 1 | -0/+4 |
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| * | | Comment out | Eddie Hung | 2019-04-09 | 1 | -1/+1 |
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| * | | Add support for synth_xilinx -abc9 and ignore abc9 -dress opt | Eddie Hung | 2019-04-09 | 2 | -1/+14 |
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| * | More space fixing | Eddie Hung | 2019-04-08 | 1 | -2/+2 |
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| * | Fix spacing | Eddie Hung | 2019-04-08 | 1 | -29/+29 |
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| * | Merge branch 'master' into xaig | Eddie Hung | 2019-04-08 | 115 | -710/+5842 |
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| | * | Merge pull request #919 from YosysHQ/multiport_transp | Clifford Wolf | 2019-04-08 | 1 | -1/+2 |
| | |\ | | | | | | | memory_bram: Fix multiport make_transp | ||||
| | | * | memory_bram: Fix multiport make_transp | David Shah | 2019-04-07 | 1 | -1/+2 |
| | |/ | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| | * | Add "read_ilang -lib" | Clifford Wolf | 2019-04-05 | 5 | -3/+39 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | Added missing argument checking to "mutate" command | Clifford Wolf | 2019-04-04 | 1 | -0/+32 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | Merge pull request #913 from smunaut/fix_proc_mux | Eddie Hung | 2019-04-03 | 1 | -1/+1 |
| | |\ | | | | | | | proc_mux: Fix crash when trying to optimize non-existant mux to shiftx | ||||
| | | * | proc_mux: Fix crash when trying to optimize non-existant mux to shiftx | Sylvain Munaut | 2019-04-03 | 1 | -1/+1 |
| | |/ | | | | | | | | | | | last_mux_cell can be NULL ... Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
| | * | Merge pull request #912 from YosysHQ/bram_addr_en | Clifford Wolf | 2019-04-03 | 1 | -0/+2 |
| | |\ | | | | | | | memory_bram: Consider read enable for address expansion register | ||||
| | | * | memory_bram: Consider read enable for address expansion register | David Shah | 2019-04-02 | 1 | -0/+2 |
| | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| | * | | Merge pull request #910 from ucb-bar/memupdates | Clifford Wolf | 2019-04-03 | 1 | -30/+173 |
| | |\ \ | | |/ | |/| | Refine memory support to deal with general Verilog memory definitions. | ||||
| | | * | Refine memory support to deal with general Verilog memory definitions. | Jim Lawson | 2019-04-01 | 1 | -30/+173 |
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| | * | | Merge pull request #895 from YosysHQ/pmux2shiftx | Eddie Hung | 2019-04-02 | 1 | -0/+28 |
| | |\ \ | | |/ | |/| | RFC: Add a pmux-to-shiftx optimisation to proc_mux | ||||
| | | * | Create one $shiftx per bit in width | Eddie Hung | 2019-03-25 | 1 | -10/+17 |
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| | | * | Add a pmux-to-shiftx optimisation to proc_mux | Eddie Hung | 2019-03-23 | 1 | -0/+21 |
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| | * | | Merge pull request #907 from YosysHQ/clifford/fix906 | Clifford Wolf | 2019-03-30 | 1 | -0/+2 |
| | |\ \ | | | | | | | | | Build Verilog parser with -DYYMAXDEPTH=100000 | ||||
| | | * | | Build Verilog parser with -DYYMAXDEPTH=100000, fixes #906 | Clifford Wolf | 2019-03-29 | 1 | -0/+2 |
| | |/ / | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | | Merge pull request #901 from trcwm/libertyfixes | Clifford Wolf | 2019-03-28 | 4 | -9/+151 |
| | |\ \ | | | | | | | | | Libertyfixes: accept superfluous ; at end of group. | ||||
| | | * | | Liberty file parser now accepts superfluous ; | Niels Moseley | 2019-03-27 | 1 | -1/+1 |
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| | | * | | Liberty file parser now accepts superfluous ; | Niels Moseley | 2019-03-27 | 1 | -1/+1 |
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| | | * | | Liberty file parser now accepts superfluous ; | Niels Moseley | 2019-03-27 | 4 | -9/+151 |
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| | * | | | Merge pull request #903 from YosysHQ/bram_reset_transp | Clifford Wolf | 2019-03-28 | 1 | -0/+1 |
| | |\ \ \ | | |/ / | |/| | | memory_bram: Reset make_transp when growing read ports | ||||
| | | * | | memory_bram: Reset make_transp when growing read ports | David Shah | 2019-03-27 | 1 | -0/+1 |
| | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| | * | | | Add "read -verific" and "read -noverific" | Clifford Wolf | 2019-03-27 | 1 | -6/+28 |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | | | Add "rename -output" | Clifford Wolf | 2019-03-27 | 1 | -3/+23 |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | | | Improve "rename" help message | Clifford Wolf | 2019-03-27 | 1 | -0/+6 |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | | | Add "cutpoint -undef" | Clifford Wolf | 2019-03-26 | 1 | -10/+14 |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | | | Add "hdlname" attribute | Clifford Wolf | 2019-03-26 | 2 | -0/+5 |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | | | Fix "verific -extnets" for more complex situations | Clifford Wolf | 2019-03-26 | 2 | -15/+93 |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | | | Add "cutpoint" pass | Clifford Wolf | 2019-03-25 | 2 | -0/+165 |
| | |/ / | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | | Merge pull request #896 from YosysHQ/transp_fixes | Clifford Wolf | 2019-03-25 | 1 | -9/+16 |
| | |\ \ | | | | | | | | | memory_bram: Fix multiclock make_transp | ||||
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index : iCE40/yosys | |
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