iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Update doc for synth_xilinx	Eddie Hung	2019-04-10	1	-7/+8
*	Merge branch 'xaig' into xc7mux	Eddie Hung	2019-04-10	1	-24/+21
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\| *	parse_aiger() to rename all $lut cells after "clean"	Eddie Hung	2019-04-10	1	-24/+21
* \|	ff_map.v after abc	Eddie Hung	2019-04-10	1	-5/+5
* \|	Tidy up	Eddie Hung	2019-04-10	1	-1/+1
* \|	Move map_cells to before map_luts	Eddie Hung	2019-04-10	1	-11/+12
* \|	WIP for $shiftx to wide mux	Eddie Hung	2019-04-10	1	-1/+63
* \|	Update LUT delays	Eddie Hung	2019-04-10	1	-11/+8
* \|	Add cells.lut to techlibs/xilinx/	Eddie Hung	2019-04-09	2	-0/+16
* \|	synth_xilinx to call abc with -lut +/xilinx/cells.lut	Eddie Hung	2019-04-09	1	-2/+2
* \|	Add delays to cells.box	Eddie Hung	2019-04-09	1	-4/+12
* \|	Add "-lut <file>" support to abc9	Eddie Hung	2019-04-09	1	-13/+31
* \|	synth_xilinx with abc9 to use -box	Eddie Hung	2019-04-09	1	-1/+4
* \|	Add techlibs/xilinx/cells.box	Eddie Hung	2019-04-09	2	-0/+6
* \|	Add "-box" option to abc9	Eddie Hung	2019-04-09	1	-7/+22
* \|	Add 'setundef -zero' call prior to aigmap in abc9	Eddie Hung	2019-04-09	1	-0/+4
* \|	Comment out	Eddie Hung	2019-04-09	1	-1/+1
* \|	Add support for synth_xilinx -abc9 and ignore abc9 -dress opt	Eddie Hung	2019-04-09	2	-1/+14
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*	More space fixing	Eddie Hung	2019-04-08	1	-2/+2
*	Fix spacing	Eddie Hung	2019-04-08	1	-29/+29
*	Merge branch 'master' into xaig	Eddie Hung	2019-04-08	115	-710/+5842
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\| *	Merge pull request #919 from YosysHQ/multiport_transp	Clifford Wolf	2019-04-08	1	-1/+2
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\| \| *	memory_bram: Fix multiport make_transp	David Shah	2019-04-07	1	-1/+2
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\| *	Add "read_ilang -lib"	Clifford Wolf	2019-04-05	5	-3/+39
\| *	Added missing argument checking to "mutate" command	Clifford Wolf	2019-04-04	1	-0/+32
\| *	Merge pull request #913 from smunaut/fix_proc_mux	Eddie Hung	2019-04-03	1	-1/+1
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\| \| *	proc_mux: Fix crash when trying to optimize non-existant mux to shiftx	Sylvain Munaut	2019-04-03	1	-1/+1
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\| *	Merge pull request #912 from YosysHQ/bram_addr_en	Clifford Wolf	2019-04-03	1	-0/+2
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\| \| *	memory_bram: Consider read enable for address expansion register	David Shah	2019-04-02	1	-0/+2
\| * \|	Merge pull request #910 from ucb-bar/memupdates	Clifford Wolf	2019-04-03	1	-30/+173
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\| \| *	Refine memory support to deal with general Verilog memory definitions.	Jim Lawson	2019-04-01	1	-30/+173
\| * \|	Merge pull request #895 from YosysHQ/pmux2shiftx	Eddie Hung	2019-04-02	1	-0/+28
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\| \| *	Create one $shiftx per bit in width	Eddie Hung	2019-03-25	1	-10/+17
\| \| *	Add a pmux-to-shiftx optimisation to proc_mux	Eddie Hung	2019-03-23	1	-0/+21
\| * \|	Merge pull request #907 from YosysHQ/clifford/fix906	Clifford Wolf	2019-03-30	1	-0/+2
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\| \| * \|	Build Verilog parser with -DYYMAXDEPTH=100000, fixes #906	Clifford Wolf	2019-03-29	1	-0/+2
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\| * \|	Merge pull request #901 from trcwm/libertyfixes	Clifford Wolf	2019-03-28	4	-9/+151
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\| \| * \|	Liberty file parser now accepts superfluous ;	Niels Moseley	2019-03-27	1	-1/+1
\| \| * \|	Liberty file parser now accepts superfluous ;	Niels Moseley	2019-03-27	1	-1/+1
\| \| * \|	Liberty file parser now accepts superfluous ;	Niels Moseley	2019-03-27	4	-9/+151
\| * \| \|	Merge pull request #903 from YosysHQ/bram_reset_transp	Clifford Wolf	2019-03-28	1	-0/+1
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\| \| * \|	memory_bram: Reset make_transp when growing read ports	David Shah	2019-03-27	1	-0/+1
\| * \| \|	Add "read -verific" and "read -noverific"	Clifford Wolf	2019-03-27	1	-6/+28
\| * \| \|	Add "rename -output"	Clifford Wolf	2019-03-27	1	-3/+23
\| * \| \|	Improve "rename" help message	Clifford Wolf	2019-03-27	1	-0/+6
\| * \| \|	Add "cutpoint -undef"	Clifford Wolf	2019-03-26	1	-10/+14
\| * \| \|	Add "hdlname" attribute	Clifford Wolf	2019-03-26	2	-0/+5
\| * \| \|	Fix "verific -extnets" for more complex situations	Clifford Wolf	2019-03-26	2	-15/+93
\| * \| \|	Add "cutpoint" pass	Clifford Wolf	2019-03-25	2	-0/+165
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\| * \|	Merge pull request #896 from YosysHQ/transp_fixes	Clifford Wolf	2019-03-25	1	-9/+16
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