| Commit message (Expand) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| * | | | | | | | | Merge branch 'master' into eddie/xilinx_srl | Eddie Hung | 2019-08-26 | 4 | -28/+125 | |
| |\| | | | | | | | ||||||
| | * | | | | | | | Remove dupe in CHANGELOG, missing end quote | Eddie Hung | 2019-08-26 | 1 | -2/+1 | |
| | * | | | | | | | Merge tag 'yosys-0.9' | Clifford Wolf | 2019-08-26 | 2 | -11/+107 | |
| | |\ \ \ \ \ \ \ | ||||||
| | | * | | | | | | | Yosys 0.9 | Clifford Wolf | 2019-08-26 | 1 | -1/+1 | |
| | | * | | | | | | | Revert earliest to gcc-4.8, compile iverilog with default compiler | Eddie Hung | 2019-08-23 | 2 | -3/+3 | |
| | | * | | | | | | | Revert "Bump to gcc-5 as `__warn_memset_zero_len' symbol not in 16.04!?!" | Eddie Hung | 2019-08-23 | 1 | -5/+3 | |
| | | * | | | | | | | Remove .0 from clang-8.0 | Eddie Hung | 2019-08-23 | 1 | -2/+2 | |
| | | * | | | | | | | Bump to gcc-5 as `__warn_memset_zero_len' symbol not in 16.04!?! | Eddie Hung | 2019-08-23 | 1 | -3/+5 | |
| | | * | | | | | | | bionic -> xenial as its on whitelist | Eddie Hung | 2019-08-23 | 1 | -1/+1 | |
| | | * | | | | | | | Bump gcc from 4.8 to 4.9 as undefined reference | Eddie Hung | 2019-08-23 | 1 | -35/+7 | |
| | | * | | | | | | | Make macOS depenency clear | Miodrag Milanovic | 2019-08-23 | 1 | -2/+5 | |
| | | * | | | | | | | do not require boost if pyosys is not used | Miodrag Milanovic | 2019-08-22 | 1 | -0/+2 | |
| | | * | | | | | | | require tcl-tk in Brewfile | Chris Shucksmith | 2019-08-22 | 1 | -0/+1 | |
| | | * | | | | | | | Bump year in copyright notice | Clifford Wolf | 2019-08-22 | 3 | -3/+3 | |
| | | * | | | | | | | Visual Studio build fix | Miodrag Milanovic | 2019-08-02 | 1 | -0/+1 | |
| | | * | | | | | | | Fix linking issue for new mxe and pthread | Miodrag Milanovic | 2019-08-02 | 1 | -1/+2 | |
| | | * | | | | | | | Fix yosys linking for mxe | Miodrag Milanovic | 2019-08-02 | 1 | -1/+1 | |
| | | * | | | | | | | New mxe hacks needed to support 2ca237e | Miodrag Milanovic | 2019-08-02 | 1 | -0/+4 | |
| | | * | | | | | | | Fix formatting for msys2 mingw build using GetSize | Miodrag Milanovic | 2019-08-02 | 8 | -17/+20 | |
| | | * | | | | | | | Update CHANGELOG | David Shah | 2019-07-26 | 1 | -10/+101 | |
| | | * | | | | | | | Merge pull request #1175 from whitequark/write_verilog-fix-case-attr-position | Clifford Wolf | 2019-07-09 | 1 | -3/+2 | |
| | | * | | | | | | | Update CHANGELOG | David Shah | 2019-07-09 | 1 | -0/+1 | |
| | | * | | | | | | | Merge pull request #1163 from whitequark/more-case-attrs | Clifford Wolf | 2019-07-09 | 3 | -16/+28 | |
| | | * | | | | | | | Merge pull request #1162 from whitequark/rtlil-case-attrs | Clifford Wolf | 2019-07-09 | 3 | -5/+15 | |
| | | * | | | | | | | Merge pull request #1159 from btut/fix/1090_segfault_cell_and_wire | Clifford Wolf | 2019-07-09 | 1 | -0/+3 | |
| | | * | | | | | | | Merge pull request #1147 from YosysHQ/clifford/fix1144 | Clifford Wolf | 2019-07-09 | 3 | -82/+26 | |
| | | * | | | | | | | Merge pull request #1154 from whitequark/manual-sync-always | Clifford Wolf | 2019-07-09 | 1 | -2/+3 | |
| | | * | | | | | | | Merge pull request #1153 from YosysHQ/dave/fix_multi_mux | David Shah | 2019-07-09 | 3 | -3/+25 | |
| | | * | | | | | | | Fix read_verilog assert/assume/etc on default case label, fixes YosysHQ/Symbi... | Clifford Wolf | 2019-07-09 | 1 | -0/+2 | |
| | | * | | | | | | | autotest.sh to define _AUTOTB when test_autotb | Eddie Hung | 2019-07-09 | 1 | -1/+1 | |
| | | * | | | | | | | Merge pull request #1146 from gsomlo/gls-test-abc-ext | Clifford Wolf | 2019-07-09 | 4 | -8/+29 | |
| | | * | | | | | | | Checkout yosys-0.9-rc branch of yosys-tests | Eddie Hung | 2019-07-02 | 1 | -1/+1 | |
| | | * | | | | | | | Add missing CHANGELOG entries | Eddie Hung | 2019-06-28 | 1 | -0/+3 | |
| | * | | | | | | | | Merge pull request #1112 from acw1251/pyosys_sigsig_issue | Clifford Wolf | 2019-08-25 | 1 | -16/+10 | |
| | |\ \ \ \ \ \ \ \ | ||||||
| | | * | | | | | | | | Fixed pyosys commands returning RTLIL::SigSig | acw1251 | 2019-06-19 | 1 | -16/+10 | |
| | * | | | | | | | | | Merge pull request #1327 from YosysHQ/clifford/pmgen | Clifford Wolf | 2019-08-24 | 5 | -32/+280 | |
| | |\ \ \ \ \ \ \ \ \ | ||||||
| | | * | | | | | | | | | indo -> into | Eddie Hung | 2019-08-23 | 1 | -1/+1 | |
| | * | | | | | | | | | | Add undocumented feature | Eddie Hung | 2019-08-23 | 1 | -0/+8 | |
| | | |_|_|_|_|_|_|/ / | |/| | | | | | | | | ||||||
| * | | | | | | | | | | Create new $__XILINX_SHREG_ cell for variable length too | Eddie Hung | 2019-08-23 | 1 | -31/+30 | |
| * | | | | | | | | | | Do not allow Q of last cell of variable length SRL to be (* keep *) | Eddie Hung | 2019-08-23 | 1 | -0/+1 | |
| * | | | | | | | | | | Also add first.Q to chain_bits since variable length | Eddie Hung | 2019-08-23 | 1 | -0/+1 | |
| * | | | | | | | | | | Do not enforce !EN_POLARITY on $dffe | Eddie Hung | 2019-08-23 | 1 | -2/+0 | |
| * | | | | | | | | | | Create new cell for fixed length SRL | Eddie Hung | 2019-08-23 | 1 | -14/+22 | |
| * | | | | | | | | | | Cleanup FDRE matching | Eddie Hung | 2019-08-23 | 1 | -45/+19 | |
| * | | | | | | | | | | Oops don't need a finally block | Eddie Hung | 2019-08-23 | 1 | -5/+0 | |
| * | | | | | | | | | | Keep track of bits in variable length chain, to check for taps | Eddie Hung | 2019-08-23 | 1 | -0/+12 | |
| * | | | | | | | | | | Don't forget $dff has no EN | Eddie Hung | 2019-08-23 | 1 | -2/+4 | |
| * | | | | | | | | | | Same for variable length | Eddie Hung | 2019-08-23 | 1 | -2/+10 | |
| * | | | | | | | | | | Filter on en_port for fixed length | Eddie Hung | 2019-08-23 | 1 | -4/+24 | |
| * | | | | | | | | | | Check clock is consistent | Eddie Hung | 2019-08-23 | 1 | -5/+25 | |
 |
index : iCE40/yosys | |
| [no description] |
| aboutsummaryrefslogtreecommitdiffstats |