aboutsummaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
...
| | * | | | | reg_wire_error test needs the -sv flag so it is run via a script so it had ↵Udi Finkelstein2018-06-052-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | to be moved out of the tests/simple dir that only runs Verilog files
| | * | | | | This PR should be the base for discussion, do not merge it yet!Udi Finkelstein2018-03-116-4/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It correctly detects reg/wire mix and incorrect use on blocking,nonblocking assignments within blocks and assign statements. What it DOES'T do: Detect registers connected to output ports of instances. Where it FAILS: memorty nonblocking assignments causes spurious (I assume??) errors on yosys-generated "_ADDR", "_DATA", "EN" signals. You can test it with tests/simple/reg_wire_error.v (look inside for the comments to enable/disable specific lines)
| * | | | | | Merge pull request #562 from udif/pr_fix_illegal_port_declClifford Wolf2018-08-151-3/+6
| |\ \ \ \ \ \ | | | | | | | | | | | | | | | | Detect illegal port declaration, e.g input/output/inout keyword must …
| | * | | | | | Detect illegal port declaration, e.g input/output/inout keyword must be the ↵Udi Finkelstein2018-06-061-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | first.
| * | | | | | | Fix use of signed integers in JSON back-endClifford Wolf2018-08-141-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | | | Merge pull request #602 from litghost/add_eblif_extensionClifford Wolf2018-08-141-0/+2
| |\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | Map .eblif extension as blif.
| | * | | | | | | Map .eblif extension as blif.litghost2018-08-131-0/+2
| | | |_|/ / / / | | |/| | | | | | | | | | | | | | | | | | | | | Signed-off-by: litghost <537074+litghost@users.noreply.github.com>
| * | | | | | | Fixed use of char array for string in blifparse error handlingClifford Wolf2018-08-081-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | | | Merge pull request #596 from litghost/extend_blif_parserClifford Wolf2018-08-081-5/+35
| |\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | #565 Add BLIF parsing support for .conn and .cname
| | * | | | | | | Report error reason on same line as syntax error.litghost2018-08-081-6/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: litghost <537074+litghost@users.noreply.github.com>
| | * | | | | | | Use log_warning which does not immediately terminate.litghost2018-08-031-3/+3
| | | | | | | | |
| | * | | | | | | Add BLIF parsing support for .conn and .cnamelitghost2018-08-021-3/+30
| | |/ / / / / /
| * | | | | | | Merge pull request #600 from jpathy/patch-1Clifford Wolf2018-08-061-1/+1
| |\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | Use `realpath`
| | * | | | | | | Use `realpath` jpathy2018-08-061-1/+1
| | |/ / / / / / | | | | | | | | | | | | | | | | Use `os.path.realpath` instead to make sure symlinks are followed. This is also required to work for nix package manager.
| * | | | | | | Merge pull request #599 from kbeckmann/kbeckmann/fix_readme_quotesClifford Wolf2018-08-061-1/+1
| |\ \ \ \ \ \ \ | | |/ / / / / / | |/| | | | | | readme: Fix formatting of a keyword
| | * | | | | | readme: Fix formatting of a keywordKonrad Beckmann2018-08-061-1/+1
| |/ / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | Single quotes were used instead of backticks leading to incorrect formatting.
| * | | | | | Verific: Produce errors for instantiating unknown moduleClifford Wolf2018-07-221-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Because if the unknown module is connected to any constants, Verific will actually break all constants in the same module, even if they have nothing to do structurally with that instance of an unknown module. Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | | Add missing <deque> include (MSVC build fix)Clifford Wolf2018-07-221-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | | Upodate ABC to git rev ae6716bClifford Wolf2018-07-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | | Add missing -lz to MXE buildClifford Wolf2018-07-221-1/+1
| | |_|/ / / | |/| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | Merge pull request #586 from hzeller/more-sourcepos-loggingClifford Wolf2018-07-204-137/+131
| |\ \ \ \ \ | | | | | | | | | | | | | | Convert more log_error() to log_file_error() where possible.
| | * | | | | Convert more log_error() to log_file_error() where possible.Henner Zeller2018-07-204-137/+131
| |/ / / / / | | | | | | | | | | | | | | | | | | | | | | | | Mostly statements that span over multiple lines and haven't been caught with the previous conversion.
| * | | | | Merge pull request #585 from hzeller/use-file-warning-errorClifford Wolf2018-07-203-82/+79
| |\ \ \ \ \ | | | | | | | | | | | | | | Use log_file_warning(), log_file_error() functions
| | * | | | | Use log_file_warning(), log_file_error() functions.Henner Zeller2018-07-203-82/+79
| |/ / / / / | | | | | | | | | | | | | | | | | | Wherever we can report a source-level location.
| * | | | | Merge pull request #584 from hzeller/provide-source-location-loggingClifford Wolf2018-07-203-47/+47
| |\ \ \ \ \ | | | | | | | | | | | | | | Provide source-location logging.
| | * | | | | Provide source-location logging.Henner Zeller2018-07-193-47/+47
| |/ / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | o Provide log_file_warning() and log_file_error() that prefix the log message with <filename>:<lineno>: to be easily picked up by IDEs that need to step through errors. o Simplify some duplicate logging code in kernel/log.cc o Use the new log functions in genrtlil.
| * | | | | Add async2sync passClifford Wolf2018-07-192-0/+148
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | | | | * Merge pull request #2 from YosysHQ/masterAman Goel2018-07-1813-9/+1242
| | | | | |\ | | |_|_|_|/ | |/| | | | Merging with official repo
| * | | | | Fix handling of eventually properties in verific importerClifford Wolf2018-07-171-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | Fix verific -vlog-incdir and -vlog-libdir handlingClifford Wolf2018-07-161-2/+13
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | Merge pull request #581 from daveshah1/ecp5Clifford Wolf2018-07-1610-3/+1200
| |\ \ \ \ \ | | | | | | | | | | | | | | Adding ECP5 synthesis target
| | * | | | | ecp5: Fixing miscellaneous sim model issuesDavid Shah2018-07-161-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| | * | | | | ecp5: Fixing 'X' issues with LUT simulation modelsDavid Shah2018-07-161-6/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| | * | | | | ecp5: ECP5 synthesis fixesDavid Shah2018-07-163-15/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| | * | | | | ecp5: Adding synchronous set/reset supportDavid Shah2018-07-145-24/+197
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| | * | | | | ecp5: Add DRAM match ruleDavid Shah2018-07-131-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| | * | | | | ecp5: Cells and mappings fixesDavid Shah2018-07-132-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| | * | | | | ecp5: Fixing arith_mapDavid Shah2018-07-131-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| | * | | | | ecp5: Initial arith_map implementationDavid Shah2018-07-133-6/+80
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| | * | | | | ecp5: Adding basic synth_ecp5 based on synth_ice40David Shah2018-07-133-7/+345
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| | * | | | | ecp5: Adding DFF mapsDavid Shah2018-07-132-1/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| | * | | | | ecp5: Adding DRAM mapDavid Shah2018-07-133-1/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| | * | | | | ecp5: Adding basic cells_sim and mapper for LUTs up to LUT7David Shah2018-07-132-0/+473
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * | | | | | Fix "read -incdir"Clifford Wolf2018-07-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | | Merge branch 'master' of github.com:YosysHQ/yosysClifford Wolf2018-07-161-2/+6
| |\ \ \ \ \ \
| | * | | | | | Merge pull request #580 from daveshah1/ice40_nxClifford Wolf2018-07-131-2/+6
| |/| | | | | | |/| |/ / / / / | | | | | | | ice40: Add CIN_CONST and CIN_SET parameters to ICESTORM_LC
| | * / / / / ice40: Add CIN_CONST and CIN_SET parameters to ICESTORM_LCDavid Shah2018-07-131-2/+6
| |/ / / / / |/| | | | | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * | | | | Add "read -incdir"Clifford Wolf2018-07-161-0/+19
|/ / / / / | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | | | * Merge branch 'YosysHQ-master'Aman Goel2018-07-0428-189/+1348
| | | | |\
| | | | | * Merging with official repoAman Goel2018-07-0428-189/+1348
| | | | |/| | |_|_|_|/ |/| | | |
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-10 08:26:35 +0000