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| author | Clifford Wolf <clifford@clifford.at> | 2018-07-16 15:32:38 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-07-16 15:32:38 +0200 |
| commit | ee68b4d96388f31321fbe7d924b00eb9532aed6b (patch) | |
| tree | f95f551abd0cfcf1e22c54bf2c8727b7cf90c67a | |
| parent | f39b897545c0f9b4d02c77cc7b6cd2a3bfc6082f (diff) | |
| parent | db4514944d2a2f0281e833677f708148497b9792 (diff) | |
| download | yosys-ee68b4d96388f31321fbe7d924b00eb9532aed6b.tar.gz yosys-ee68b4d96388f31321fbe7d924b00eb9532aed6b.tar.bz2 yosys-ee68b4d96388f31321fbe7d924b00eb9532aed6b.zip | |
Merge branch 'master' of github.com:YosysHQ/yosys
| -rw-r--r-- | techlibs/ice40/cells_sim.v | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index 45a02111f..9f73aeb07 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -657,7 +657,12 @@ module ICESTORM_LC ( parameter [0:0] SET_NORESET = 0; parameter [0:0] ASYNC_SR = 0; - assign COUT = CARRY_ENABLE ? (I1 && I2) || ((I1 || I2) && CIN) : 1'bx; + parameter [0:0] CIN_CONST = 0; + parameter [0:0] CIN_SET = 0; + + wire mux_cin = CIN_CONST ? CIN_SET : CIN; + + assign COUT = CARRY_ENABLE ? (I1 && I2) || ((I1 || I2) && mux_cin) : 1'bx; wire [7:0] lut_s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0]; wire [3:0] lut_s2 = I2 ? lut_s3[ 7:4] : lut_s3[3:0]; @@ -1226,4 +1231,3 @@ module SB_IO_OD ( endgenerate `endif endmodule - |