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| author | Konrad Beckmann <konrad.beckmann@gmail.com> | 2018-08-06 13:30:33 +0900 |
|---|---|---|
| committer | Konrad Beckmann <konrad.beckmann@gmail.com> | 2018-08-06 13:33:02 +0900 |
| commit | da53206cd4b1e32d8bf29bb33cdfec81d614525e (patch) | |
| tree | c8f9adf27b2a218c73818f3b6fc0dd4d4824892b | |
| parent | e275692e84c935d0cdf42c2a4adf7ac949a88132 (diff) | |
| download | yosys-da53206cd4b1e32d8bf29bb33cdfec81d614525e.tar.gz yosys-da53206cd4b1e32d8bf29bb33cdfec81d614525e.tar.bz2 yosys-da53206cd4b1e32d8bf29bb33cdfec81d614525e.zip | |
readme: Fix formatting of a keyword
Single quotes were used instead of backticks leading to
incorrect formatting.
| -rw-r--r-- | README.md | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -389,7 +389,7 @@ Verilog Attributes and non-standard features Non-standard or SystemVerilog features for formal verification ============================================================== -- Support for ``assert``, ``assume``, ``restrict``, and ``cover'' is enabled +- Support for ``assert``, ``assume``, ``restrict``, and ``cover`` is enabled when ``read_verilog`` is called with ``-formal``. - The system task ``$initstate`` evaluates to 1 in the initial state and |