diff options
| author | Clifford Wolf <clifford@clifford.at> | 2018-07-13 14:31:38 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-07-13 14:31:38 +0200 |
| commit | db4514944d2a2f0281e833677f708148497b9792 (patch) | |
| tree | d46090966fc9939667f82b8db203c2b1d6a6d1de | |
| parent | 8b92ddb9d2635c30636b17ff3d24bc09a44b8551 (diff) | |
| parent | cd65eeb3b3a2410e6e42f35e8ab58be4276fd104 (diff) | |
| download | yosys-db4514944d2a2f0281e833677f708148497b9792.tar.gz yosys-db4514944d2a2f0281e833677f708148497b9792.tar.bz2 yosys-db4514944d2a2f0281e833677f708148497b9792.zip | |
Merge pull request #580 from daveshah1/ice40_nx
ice40: Add CIN_CONST and CIN_SET parameters to ICESTORM_LC
| -rw-r--r-- | techlibs/ice40/cells_sim.v | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index 45a02111f..9f73aeb07 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -657,7 +657,12 @@ module ICESTORM_LC ( parameter [0:0] SET_NORESET = 0; parameter [0:0] ASYNC_SR = 0; - assign COUT = CARRY_ENABLE ? (I1 && I2) || ((I1 || I2) && CIN) : 1'bx; + parameter [0:0] CIN_CONST = 0; + parameter [0:0] CIN_SET = 0; + + wire mux_cin = CIN_CONST ? CIN_SET : CIN; + + assign COUT = CARRY_ENABLE ? (I1 && I2) || ((I1 || I2) && mux_cin) : 1'bx; wire [7:0] lut_s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0]; wire [3:0] lut_s2 = I2 ? lut_s3[ 7:4] : lut_s3[3:0]; @@ -1226,4 +1231,3 @@ module SB_IO_OD ( endgenerate `endif endmodule - |