diff options
Diffstat (limited to 'techlibs/xilinx')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 138a6470f..285d63dbf 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -119,8 +119,8 @@ module FDSE (output reg Q, input C, CE, D, S); parameter [0:0] IS_S_INVERTED = 1'b0; initial Q <= INIT; generate case (|IS_C_INVERTED) - 1'b0: always @(posedge C) if (S == !IS_S_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; - 1'b1: always @(negedge C) if (S == !IS_S_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; + 1'b0: always @(posedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED; + 1'b1: always @(negedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED; endcase endgenerate endmodule |