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| author | Clifford Wolf <clifford@clifford.at> | 2015-01-24 11:03:22 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-01-24 11:03:22 +0100 |
| commit | 909a95182b6de03d6227f6331a6e60692d20203d (patch) | |
| tree | e2cf37f0b27dbf55e22c8b07cf2c4cd74498e49d /techlibs/xilinx | |
| parent | 75bbeb828ad266a7614eff2e33d0a8f9fab75ed2 (diff) | |
| download | yosys-909a95182b6de03d6227f6331a6e60692d20203d.tar.gz yosys-909a95182b6de03d6227f6331a6e60692d20203d.tar.bz2 yosys-909a95182b6de03d6227f6331a6e60692d20203d.zip | |
Fixed xilinx FDSE sim model
Diffstat (limited to 'techlibs/xilinx')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 138a6470f..285d63dbf 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -119,8 +119,8 @@ module FDSE (output reg Q, input C, CE, D, S); parameter [0:0] IS_S_INVERTED = 1'b0; initial Q <= INIT; generate case (|IS_C_INVERTED) - 1'b0: always @(posedge C) if (S == !IS_S_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; - 1'b1: always @(negedge C) if (S == !IS_S_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; + 1'b0: always @(posedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED; + 1'b1: always @(negedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED; endcase endgenerate endmodule |