diff options
author | Marcelina KoĆcielnicka <mwk@0x04.net> | 2020-04-11 16:03:19 +0200 |
---|---|---|
committer | Marcelina KoĆcielnicka <mwk@0x04.net> | 2020-04-15 17:17:48 +0200 |
commit | 53ba3cf7188883a9ef1c6c506c7b3a842dccc87b (patch) | |
tree | a974fe8ddee04385fef434ea44f53e6f4a0f0d5e /techlibs/common/simcells.v | |
parent | 7ad8b242806357599cfcbd228cef5c331935ef7c (diff) | |
download | yosys-53ba3cf7188883a9ef1c6c506c7b3a842dccc87b.tar.gz yosys-53ba3cf7188883a9ef1c6c506c7b3a842dccc87b.tar.bz2 yosys-53ba3cf7188883a9ef1c6c506c7b3a842dccc87b.zip |
Fix the truth table for $_SR_* cells.
This brings the documented behavior for these cells in line with
$_DFFSR_* and $_DLATCHSR_*, which is that R has priority over S.
The models were already reflecting that behavior.
Also get rid of sim-synth mismatch in the models while we're at it.
Diffstat (limited to 'techlibs/common/simcells.v')
-rw-r--r-- | techlibs/common/simcells.v | 36 |
1 files changed, 16 insertions, 20 deletions
diff --git a/techlibs/common/simcells.v b/techlibs/common/simcells.v index 2bac78d38..157e8d23b 100644 --- a/techlibs/common/simcells.v +++ b/techlibs/common/simcells.v @@ -469,15 +469,14 @@ endmodule //- //- Truth table: S R | Q //- -----+--- -//- 0 0 | x -//- 0 1 | 1 -//- 1 0 | 0 -//- 1 1 | y +//- - 0 | 0 +//- 0 - | 1 +//- - - | q //- module \$_SR_NN_ (S, R, Q); input S, R; output reg Q; -always @(negedge S, negedge R) begin +always @* begin if (R == 0) Q <= 0; else if (S == 0) @@ -493,15 +492,14 @@ endmodule //- //- Truth table: S R | Q //- -----+--- -//- 0 1 | x -//- 0 0 | 1 -//- 1 1 | 0 -//- 1 0 | y +//- - 1 | 0 +//- 0 - | 1 +//- - - | q //- module \$_SR_NP_ (S, R, Q); input S, R; output reg Q; -always @(negedge S, posedge R) begin +always @* begin if (R == 1) Q <= 0; else if (S == 0) @@ -517,15 +515,14 @@ endmodule //- //- Truth table: S R | Q //- -----+--- -//- 1 0 | x -//- 1 1 | 1 -//- 0 0 | 0 -//- 0 1 | y +//- - 0 | 0 +//- 1 - | 1 +//- - - | q //- module \$_SR_PN_ (S, R, Q); input S, R; output reg Q; -always @(posedge S, negedge R) begin +always @* begin if (R == 0) Q <= 0; else if (S == 1) @@ -541,15 +538,14 @@ endmodule //- //- Truth table: S R | Q //- -----+--- -//- 1 1 | x -//- 1 0 | 1 -//- 0 1 | 0 -//- 0 0 | y +//- - 1 | 0 +//- 1 - | 1 +//- - - | q //- module \$_SR_PP_ (S, R, Q); input S, R; output reg Q; -always @(posedge S, posedge R) begin +always @* begin if (R == 1) Q <= 0; else if (S == 1) |