From 53ba3cf7188883a9ef1c6c506c7b3a842dccc87b Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Sat, 11 Apr 2020 16:03:19 +0200
Subject: Fix the truth table for $_SR_* cells.

This brings the documented behavior for these cells in line with
$_DFFSR_* and $_DLATCHSR_*, which is that R has priority over S.
The models were already reflecting that behavior.

Also get rid of sim-synth mismatch in the models while we're at it.
---
 techlibs/common/simcells.v | 36 ++++++++++++++++--------------------
 1 file changed, 16 insertions(+), 20 deletions(-)

(limited to 'techlibs/common/simcells.v')

diff --git a/techlibs/common/simcells.v b/techlibs/common/simcells.v
index 2bac78d38..157e8d23b 100644
--- a/techlibs/common/simcells.v
+++ b/techlibs/common/simcells.v
@@ -469,15 +469,14 @@ endmodule
 //-
 //- Truth table:    S R | Q
 //-                -----+---
-//-                 0 0 | x
-//-                 0 1 | 1
-//-                 1 0 | 0
-//-                 1 1 | y
+//-                 - 0 | 0
+//-                 0 - | 1
+//-                 - - | q
 //-
 module \$_SR_NN_ (S, R, Q);
 input S, R;
 output reg Q;
-always @(negedge S, negedge R) begin
+always @* begin
 	if (R == 0)
 		Q <= 0;
 	else if (S == 0)
@@ -493,15 +492,14 @@ endmodule
 //-
 //- Truth table:    S R | Q
 //-                -----+---
-//-                 0 1 | x
-//-                 0 0 | 1
-//-                 1 1 | 0
-//-                 1 0 | y
+//-                 - 1 | 0
+//-                 0 - | 1
+//-                 - - | q
 //-
 module \$_SR_NP_ (S, R, Q);
 input S, R;
 output reg Q;
-always @(negedge S, posedge R) begin
+always @* begin
 	if (R == 1)
 		Q <= 0;
 	else if (S == 0)
@@ -517,15 +515,14 @@ endmodule
 //-
 //- Truth table:    S R | Q
 //-                -----+---
-//-                 1 0 | x
-//-                 1 1 | 1
-//-                 0 0 | 0
-//-                 0 1 | y
+//-                 - 0 | 0
+//-                 1 - | 1
+//-                 - - | q
 //-
 module \$_SR_PN_ (S, R, Q);
 input S, R;
 output reg Q;
-always @(posedge S, negedge R) begin
+always @* begin
 	if (R == 0)
 		Q <= 0;
 	else if (S == 1)
@@ -541,15 +538,14 @@ endmodule
 //-
 //- Truth table:    S R | Q
 //-                -----+---
-//-                 1 1 | x
-//-                 1 0 | 1
-//-                 0 1 | 0
-//-                 0 0 | y
+//-                 - 1 | 0
+//-                 1 - | 1
+//-                 - - | q
 //-
 module \$_SR_PP_ (S, R, Q);
 input S, R;
 output reg Q;
-always @(posedge S, posedge R) begin
+always @* begin
 	if (R == 1)
 		Q <= 0;
 	else if (S == 1)
-- 
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