diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-05-01 16:26:43 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-05-01 16:26:43 -0700 |
| commit | f86d153cef724af9d30e4139783a7e14d7ba0a19 (patch) | |
| tree | 1c2cd09407cbeef2f68c19f9bcfb95566355fa01 /frontends | |
| parent | acafcdc94dc148b2bf9c8faef173e5b2b54e1ac5 (diff) | |
| parent | 7a0af004a0a4dc3831997f0845d40fc3ea514281 (diff) | |
| download | yosys-f86d153cef724af9d30e4139783a7e14d7ba0a19.tar.gz yosys-f86d153cef724af9d30e4139783a7e14d7ba0a19.tar.bz2 yosys-f86d153cef724af9d30e4139783a7e14d7ba0a19.zip | |
Merge branch 'master' of github.com:YosysHQ/yosys
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/ast/simplify.cc | 9 | ||||
| -rw-r--r-- | frontends/verilog/verilog_frontend.cc | 4 |
2 files changed, 11 insertions, 2 deletions
diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 3e453bd7f..4d4b9dfe1 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -1172,6 +1172,15 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, varbuf->children[0] = buf; } +#if 0 + if (type == AST_FOR) { + AstNode *buf = next_ast->clone(); + delete buf->children[1]; + buf->children[1] = varbuf->children[0]->clone(); + current_block->children.insert(current_block->children.begin() + current_block_idx++, buf); + } +#endif + current_scope[varbuf->str] = backup_scope_varbuf; delete varbuf; delete_children(); diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc index ed6ce2ecb..9e624d355 100644 --- a/frontends/verilog/verilog_frontend.cc +++ b/frontends/verilog/verilog_frontend.cc @@ -242,8 +242,6 @@ struct VerilogFrontend : public Frontend { nowb_mode = false; default_nettype_wire = true; - log_header(design, "Executing Verilog-2005 frontend.\n"); - args.insert(args.begin()+1, verilog_defaults.begin(), verilog_defaults.end()); size_t argidx; @@ -415,6 +413,8 @@ struct VerilogFrontend : public Frontend { } extra_args(f, filename, args, argidx); + log_header(design, "Executing Verilog-2005 frontend: %s\n", filename.c_str()); + log("Parsing %s%s input from `%s' to AST representation.\n", formal_mode ? "formal " : "", sv_mode ? "SystemVerilog" : "Verilog", filename.c_str()); |