From 9af825e31e493bec6f0d86b8f30aeee436ed50df Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 30 Apr 2019 15:03:32 +0200 Subject: Add final loop variable assignment when unrolling for-loops, fixes #968 Signed-off-by: Clifford Wolf --- frontends/ast/simplify.cc | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'frontends') diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 3e453bd7f..a342bf5d9 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -1172,6 +1172,13 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, varbuf->children[0] = buf; } + if (type == AST_FOR) { + AstNode *buf = next_ast->clone(); + delete buf->children[1]; + buf->children[1] = varbuf->children[0]->clone(); + current_block->children.insert(current_block->children.begin() + current_block_idx++, buf); + } + current_scope[varbuf->str] = backup_scope_varbuf; delete varbuf; delete_children(); -- cgit v1.2.3 From 84f3a796e1232b19674a412b5d011d208d923f5c Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 30 Apr 2019 15:35:36 +0200 Subject: Include filename in "Executing Verilog-2005 frontend" message, fixes #959 Signed-off-by: Clifford Wolf --- frontends/verilog/verilog_frontend.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'frontends') diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc index ed6ce2ecb..9e624d355 100644 --- a/frontends/verilog/verilog_frontend.cc +++ b/frontends/verilog/verilog_frontend.cc @@ -242,8 +242,6 @@ struct VerilogFrontend : public Frontend { nowb_mode = false; default_nettype_wire = true; - log_header(design, "Executing Verilog-2005 frontend.\n"); - args.insert(args.begin()+1, verilog_defaults.begin(), verilog_defaults.end()); size_t argidx; @@ -415,6 +413,8 @@ struct VerilogFrontend : public Frontend { } extra_args(f, filename, args, argidx); + log_header(design, "Executing Verilog-2005 frontend: %s\n", filename.c_str()); + log("Parsing %s%s input from `%s' to AST representation.\n", formal_mode ? "formal " : "", sv_mode ? "SystemVerilog" : "Verilog", filename.c_str()); -- cgit v1.2.3 From e35fe1344dd4c8f11632ed2a7f5b0463352a1ee4 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 30 Apr 2019 20:22:50 +0200 Subject: Disabled "final loop assignment" feature Signed-off-by: Clifford Wolf --- frontends/ast/simplify.cc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'frontends') diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index a342bf5d9..4d4b9dfe1 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -1172,12 +1172,14 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, varbuf->children[0] = buf; } +#if 0 if (type == AST_FOR) { AstNode *buf = next_ast->clone(); delete buf->children[1]; buf->children[1] = varbuf->children[0]->clone(); current_block->children.insert(current_block->children.begin() + current_block_idx++, buf); } +#endif current_scope[varbuf->str] = backup_scope_varbuf; delete varbuf; -- cgit v1.2.3