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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-06 16:51:32 -0800 |
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| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-06 16:51:32 -0800 |
| commit | 5c89dead5f481edaccd46ebc0af907544c89654f (patch) | |
| tree | c40306fef9c52f8065cf5f19b42f31b668b17526 /README.md | |
| parent | 01866a79093092bc2f8a8b20376f6cb552f76f00 (diff) | |
| parent | ce765aa4def09bd8b0161425ee40ee55f62e33ff (diff) | |
| download | yosys-5c89dead5f481edaccd46ebc0af907544c89654f.tar.gz yosys-5c89dead5f481edaccd46ebc0af907544c89654f.tar.bz2 yosys-5c89dead5f481edaccd46ebc0af907544c89654f.zip | |
Merge branch 'master' of github.com:YosysHQ/yosys
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 6 |
1 files changed, 5 insertions, 1 deletions
@@ -376,7 +376,11 @@ Verilog Attributes and non-standard features - The port attribute ``abc9_arrival`` specifies an integer (for output ports only) to be used as the arrival time of this sequential port. It can be used, for example, to specify the clk-to-Q delay of a flip-flop for consideration - during techmapping. + during `abc9` techmapping. + +- The module attribute ``abc9_flop`` is a boolean marking the module as a + flip-flop. This allows `abc9` to analyse its contents in order to perform + sequential synthesis. - The frontend sets attributes ``always_comb``, ``always_latch`` and ``always_ff`` on processes derived from SystemVerilog style always blocks |