From ece423415cbc17654c6ac81a0f4b15783c558660 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 30 Dec 2019 14:24:58 -0800 Subject: Add CHANGELOG entry, add abc9_{flop,keep} attr to README.md --- README.md | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'README.md') diff --git a/README.md b/README.md index 0250c7846..c04e2b9ec 100644 --- a/README.md +++ b/README.md @@ -378,6 +378,12 @@ Verilog Attributes and non-standard features for example, to specify the clk-to-Q delay of a flip-flop for consideration during techmapping. +- The module attribute ``abc9_flop`` is a boolean marking the module as a + whitebox that describes the synchronous behaviour of a flip-flop. + +- The cell attribute ``abc9_keep`` is a boolean indicating that this black/ + white box should be preserved through `abc9` mapping. + - The frontend sets attributes ``always_comb``, ``always_latch`` and ``always_ff`` on processes derived from SystemVerilog style always blocks according to the type of the always. These are checked for correctness in -- cgit v1.2.3 From c40b1aae42c91f200194f7f5f2caa512787ed5a3 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 1 Jan 2020 08:34:43 -0800 Subject: Restore abc9 -keepff --- README.md | 3 --- 1 file changed, 3 deletions(-) (limited to 'README.md') diff --git a/README.md b/README.md index c04e2b9ec..aab1c7d6b 100644 --- a/README.md +++ b/README.md @@ -381,9 +381,6 @@ Verilog Attributes and non-standard features - The module attribute ``abc9_flop`` is a boolean marking the module as a whitebox that describes the synchronous behaviour of a flip-flop. -- The cell attribute ``abc9_keep`` is a boolean indicating that this black/ - white box should be preserved through `abc9` mapping. - - The frontend sets attributes ``always_comb``, ``always_latch`` and ``always_ff`` on processes derived from SystemVerilog style always blocks according to the type of the always. These are checked for correctness in -- cgit v1.2.3 From ffd38cb5ea7a6b7d93a49c90bf603131f6c760af Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 6 Jan 2020 09:03:18 -0800 Subject: Reword (* abc9_flop *) description --- README.md | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'README.md') diff --git a/README.md b/README.md index aab1c7d6b..77e9410da 100644 --- a/README.md +++ b/README.md @@ -376,10 +376,11 @@ Verilog Attributes and non-standard features - The port attribute ``abc9_arrival`` specifies an integer (for output ports only) to be used as the arrival time of this sequential port. It can be used, for example, to specify the clk-to-Q delay of a flip-flop for consideration - during techmapping. + during `abc9` techmapping. - The module attribute ``abc9_flop`` is a boolean marking the module as a - whitebox that describes the synchronous behaviour of a flip-flop. + flip-flop. This allows `abc9` to analyse its contents in order to perform + sequential synthesis. - The frontend sets attributes ``always_comb``, ``always_latch`` and ``always_ff`` on processes derived from SystemVerilog style always blocks -- cgit v1.2.3