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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-06 16:50:07 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-01-06 16:50:07 -0800 |
| commit | ce765aa4def09bd8b0161425ee40ee55f62e33ff (patch) | |
| tree | 2a91632d31dab23188d6cb1b4bef16b47518cbe4 /README.md | |
| parent | 66698cb6fd0e33a27197b7412e094dc77363b5e5 (diff) | |
| parent | 98ee8c14df763973d47c8c952d462eb9407f6787 (diff) | |
| download | yosys-ce765aa4def09bd8b0161425ee40ee55f62e33ff.tar.gz yosys-ce765aa4def09bd8b0161425ee40ee55f62e33ff.tar.bz2 yosys-ce765aa4def09bd8b0161425ee40ee55f62e33ff.zip | |
Merge pull request #1181 from YosysHQ/xaig_dff
"abc9 -dff" option for sequential synthesis
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 6 |
1 files changed, 5 insertions, 1 deletions
@@ -376,7 +376,11 @@ Verilog Attributes and non-standard features - The port attribute ``abc9_arrival`` specifies an integer (for output ports only) to be used as the arrival time of this sequential port. It can be used, for example, to specify the clk-to-Q delay of a flip-flop for consideration - during techmapping. + during `abc9` techmapping. + +- The module attribute ``abc9_flop`` is a boolean marking the module as a + flip-flop. This allows `abc9` to analyse its contents in order to perform + sequential synthesis. - The frontend sets attributes ``always_comb``, ``always_latch`` and ``always_ff`` on processes derived from SystemVerilog style always blocks |