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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-22 12:30:49 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-22 16:05:12 -0700 |
| commit | 9224b3bc1721ae45abf11594b3ab9a58e50aa86f (patch) | |
| tree | cf756810ebe070fd369d9c8ac7c5693a67f0fcb7 | |
| parent | 388eb3288c907dbc8b2763ffc20b0b5fccba81ed (diff) | |
| download | yosys-9224b3bc1721ae45abf11594b3ab9a58e50aa86f.tar.gz yosys-9224b3bc1721ae45abf11594b3ab9a58e50aa86f.tar.bz2 yosys-9224b3bc1721ae45abf11594b3ab9a58e50aa86f.zip | |
Remove tech independent synthesis
| -rw-r--r-- | tests/ice40/add_sub.ys | 1 | ||||
| -rw-r--r-- | tests/ice40/adffs.ys | 10 | ||||
| -rw-r--r-- | tests/ice40/dffs.ys | 3 | ||||
| -rw-r--r-- | tests/ice40/div_mod.ys | 2 | ||||
| -rw-r--r-- | tests/ice40/latches.ys | 5 | ||||
| -rw-r--r-- | tests/ice40/memory.ys | 1 | ||||
| -rw-r--r-- | tests/ice40/mul.ys | 1 | ||||
| -rw-r--r-- | tests/ice40/mux.ys | 8 | ||||
| -rw-r--r-- | tests/ice40/tribuf.ys | 5 |
9 files changed, 20 insertions, 16 deletions
diff --git a/tests/ice40/add_sub.ys b/tests/ice40/add_sub.ys index 84f31ec53..8eeb221db 100644 --- a/tests/ice40/add_sub.ys +++ b/tests/ice40/add_sub.ys @@ -1,6 +1,5 @@ read_verilog add_sub.v hierarchy -top top -synth -flatten -run coarse # technology-independent coarse grained synthesis equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/tests/ice40/adffs.ys b/tests/ice40/adffs.ys index d58ce1a82..3c676e590 100644 --- a/tests/ice40/adffs.ys +++ b/tests/ice40/adffs.ys @@ -1,12 +1,12 @@ read_verilog adffs.v proc async2sync -synth -flatten -run coarse # technology-independent coarse grained synthesis +flatten equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 1 t:SB_DFF -select -assert-count 1 t:SB_DFFE -select -assert-count 4 t:SB_LUT4 -#select -assert-none t:SB_LUT4 t:SB_DFFR t:SB_DFFE t:$_DFFSR_NPP_ t:$_DFFSR_PPP_ %% t:* %D -write_verilog adffs_synth.v +select -assert-count 1 t:SB_DFFN +select -assert-count 2 t:SB_DFFSR +select -assert-count 7 t:SB_LUT4 +select -assert-none t:SB_DFF t:SB_DFFN t:SB_DFFSR t:SB_LUT4 %% t:* %D diff --git a/tests/ice40/dffs.ys b/tests/ice40/dffs.ys index ddd8e5734..b14346f5a 100644 --- a/tests/ice40/dffs.ys +++ b/tests/ice40/dffs.ys @@ -1,6 +1,7 @@ read_verilog dffs.v hierarchy -top top -synth -flatten -run coarse # technology-independent coarse grained synthesis +proc +flatten equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/tests/ice40/div_mod.ys b/tests/ice40/div_mod.ys index 93285cede..613cad760 100644 --- a/tests/ice40/div_mod.ys +++ b/tests/ice40/div_mod.ys @@ -1,6 +1,6 @@ read_verilog div_mod.v hierarchy -top top -synth -flatten -run coarse # technology-independent coarse grained synthesis +flatten equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/tests/ice40/latches.ys b/tests/ice40/latches.ys index 0abd7f195..fe0d1f70e 100644 --- a/tests/ice40/latches.ys +++ b/tests/ice40/latches.ys @@ -1,5 +1,6 @@ read_verilog latches.v synth_ice40 -select -assert-count 5 t:SB_LUT4 -#select -assert-none t:SB_LUT4 %% t:* %D +cd top +select -assert-count 4 t:SB_LUT4 +select -assert-none t:SB_LUT4 %% t:* %D write_verilog latches_synth.v diff --git a/tests/ice40/memory.ys b/tests/ice40/memory.ys index a0391e93d..0a8c48dca 100644 --- a/tests/ice40/memory.ys +++ b/tests/ice40/memory.ys @@ -1,4 +1,5 @@ read_verilog memory.v synth_ice40 +cd top select -assert-count 1 t:SB_RAM40_4K write_verilog memory_synth.v diff --git a/tests/ice40/mul.ys b/tests/ice40/mul.ys index adf1b3211..aec7d0b1f 100644 --- a/tests/ice40/mul.ys +++ b/tests/ice40/mul.ys @@ -1,6 +1,5 @@ read_verilog mul.v hierarchy -top top -#synth -flatten -run coarse # technology-independent coarse grained synthesis equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check same as technology-dependent fine-grained synthesis design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/tests/ice40/mux.ys b/tests/ice40/mux.ys index 9e3d87b7f..63d22001f 100644 --- a/tests/ice40/mux.ys +++ b/tests/ice40/mux.ys @@ -1,6 +1,8 @@ read_verilog mux.v -synth_ice40 +proc +flatten equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 design -load postopt -select -assert-count 20 t:SB_LUT4 -select -assert-count 1 t:SB_CARRY +cd top +select -assert-count 19 t:SB_LUT4 +select -assert-none t:SB_LUT4 %% t:* %D diff --git a/tests/ice40/tribuf.ys b/tests/ice40/tribuf.ys index 9b7ea1eab..8049a37ab 100644 --- a/tests/ice40/tribuf.ys +++ b/tests/ice40/tribuf.ys @@ -1,7 +1,8 @@ read_verilog tribuf.v hierarchy -top top -synth -flatten -run coarse # technology-independent coarse grained synthesis -equiv_opt -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis +proc +flatten +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 1 t:$_TBUF_ |