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-rw-r--r--tests/ice40/div_mod.ys2
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/ice40/div_mod.ys b/tests/ice40/div_mod.ys
index 93285cede..613cad760 100644
--- a/tests/ice40/div_mod.ys
+++ b/tests/ice40/div_mod.ys
@@ -1,6 +1,6 @@
read_verilog div_mod.v
hierarchy -top top
-synth -flatten -run coarse # technology-independent coarse grained synthesis
+flatten
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module