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* Merge branch 'master' into redist_slackEddie Hung2018-07-2414-93/+419
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| * ice40: after reviewSergiusz Bazanski2018-07-241-1/+0
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| * Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into q3k/pllSergiusz Bazanski2018-07-249-85/+44
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| | * Remove implementations of deprecated APIsDavid Shah2018-07-243-30/+0
| | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| | * ice40: Remove use of deprecated APIsDavid Shah2018-07-243-10/+10
| | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| | * Remove uphill/downhill bel pins from ice40 dbClifford Wolf2018-07-242-34/+0
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * Add bbasm target, use as passthru in iCE40 builderDavid Shah2018-07-241-5/+16
| | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| | * Add G_ARROW (for now same look as G_LINE)Clifford Wolf2018-07-241-1/+1
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * timing: Model clock to Q timesDavid Shah2018-07-241-0/+15
| | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| | * ice40: Trim BRAM constant inputs, reduces routing congestion around BRAMDavid Shah2018-07-241-0/+3
| | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| | * ice40: Fix SPRAM and other primitives in corners other than (0, 0)David Shah2018-07-241-1/+1
| | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * | ice40: fixes before reviewSergiusz Bazanski2018-07-245-45/+13
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| * | ice40: move PLL->IO from pseudo pip to second uphill belSergiusz Bazanski2018-07-243-69/+40
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| * | ice40: emit list of upbels in chipdbSergiusz Bazanski2018-07-244-16/+22
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| * | clang-formatSergiusz Bazanski2018-07-243-66/+74
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| * | ice40: A slightly nicer way to do this.Sergiusz Bazanski2018-07-241-46/+31
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| * | ice40: Move spliceLUT back to pack.ccSergiusz Bazanski2018-07-243-56/+53
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| * | ice40: Prevent placement of SB_IOs in IO blocks used by PLL outputsSergiusz Bazanski2018-07-241-0/+24
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| * | ice40: Refactor PLL/LOCK LUT splicing out into Arch::Sergiusz Bazanski2018-07-244-74/+59
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| * | ice40: Emit feed-through LUTs for PLL/LOCKSergiusz Bazanski2018-07-242-2/+159
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| * | ice40: Fail early on SB_PLL40_*_PAD cellsSergiusz Bazanski2018-07-242-0/+14
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| * | ice40: Implement emitting PLLsSergiusz Bazanski2018-07-249-16/+269
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* | Merge branch 'master' into redist_slackEddie Hung2018-07-237-156/+212
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| * Add Context::archcheck() and "nextpnr-ice40 --test"Clifford Wolf2018-07-232-40/+60
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Remove getBelsByType() APIClifford Wolf2018-07-231-14/+0
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * clangformatDavid Shah2018-07-231-2/+3
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * Add getGridDimX(), getGridDimY(), getTileDimZ() APIClifford Wolf2018-07-231-0/+6
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Bugfix in iCE40 chipdb.pyClifford Wolf2018-07-231-3/+0
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Move to new API and remove deprecatedMiodrag Milanovic2018-07-223-63/+40
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| * Add Arch::getBelPins() to generic and iCE40 archsClifford Wolf2018-07-222-0/+17
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Add Arch::getBelPinType() and Arch::getWireBelPins() in iCE40 archClifford Wolf2018-07-223-4/+57
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Rename getWireBelPin to getBelPinWireClifford Wolf2018-07-226-18/+18
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * clangformatClifford Wolf2018-07-223-8/+4
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Merge branch 'q3k/lock-2-electric-boogaloo' into 'master'Clifford Wolf2018-07-212-4/+12
| |\ | | | | | | | | | | | | Basic locking and threading for Arch/GUI See merge request SymbioticEDA/nextpnr!10
| | * Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into ↵Sergiusz Bazanski2018-07-219-543/+904
| | |\ | | | | | | | | | | | | q3k/lock-2-electric-boogaloo
| | * | Re-enable drawing Pips.Sergiusz Bazanski2018-07-201-3/+3
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| | * | clang-formatSergiusz Bazanski2018-07-201-1/+1
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| | * | Nuke IdStringDBSergiusz Bazanski2018-07-201-1/+1
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| | * | Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into ↵Sergiusz Bazanski2018-07-2016-95/+361
| | |\ \ | | | | | | | | | | | | | | | q3k/lock-2-electric-boogaloo
| | * | | WIP.Serge Bazanski2018-07-171-0/+8
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| | * | | Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into ↵Serge Bazanski2018-07-171-4/+4
| | |\ \ \ | | | | | | | | | | | | | | | | | | q3k/lock-2-electric-boogaloo
| | * \ \ \ Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into ↵Serge Bazanski2018-07-155-14/+261
| | |\ \ \ \ | | | | | | | | | | | | | | | | | | | | | q3k/lock-2-electric-boogaloo
| | * | | | | Refactor IdString functionality into IdStringDBSerge Bazanski2018-07-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This lets us more precisely control the lifetime of IdString databases in contexts/arches.
| * | | | | | Add Loc constructorsClifford Wolf2018-07-211-6/+1
| | |_|_|_|/ | |/| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* / | | | | Add Arch::getBudgetOverride() to eliminate hack for COUTEddie Hung2018-07-212-0/+7
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* | | | | Added driver and users for netsMiodrag Milanovic2018-07-211-0/+8
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* | | | | Merge branch 'router1ng' into 'master'Clifford Wolf2018-07-211-0/+1
|\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | Router1ng See merge request SymbioticEDA/nextpnr!13
| * | | | | Refactoring of router1Clifford Wolf2018-07-211-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Use source-sink pairs as jobs, not whole nets - Route nets with smallest slack first - Preserve routes for already routed source-sink pairs - Add small incentive for re-using wires Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | Map ports to netsMiodrag Milanovic2018-07-211-0/+14
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* | | | | | create io cells out of ascMiodrag Milanovic2018-07-211-0/+27
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