Add Context::archcheck() and "nextpnr-ice40 --test"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

2 files changed, 60 insertions, 40 deletions

diff --git a/ice40/chipdb.py b/ice40/chipdb.py
index 8cb51e38..0e8e3ba7 100644
--- a/ice40/chipdb.py
+++ b/ice40/chipdb.py
@@ -373,8 +373,12 @@ with open(args.filename, "r") as f:
         if line[0] == ".extra_cell":
             if len(line) >= 5:
                 mode = ("extra_cell", (line[4], int(line[1]), int(line[2]), int(line[3])))
-            else:
+            elif line[3] == "WARMBOOT":
+                mode = ("extra_cell", (line[3], int(line[1]), int(line[2]), 0))
+            elif line[3] == "PLL":
                 mode = ("extra_cell", (line[3], int(line[1]), int(line[2]), 3))
+            else:
+                assert 0
             extra_cells[mode[1]] = []
             continue
 
@@ -564,11 +568,14 @@ def add_bel_ram(x, y):
     add_bel_input(bel, wire_names[(x, y1, "ram/RCLKE")], "RCLKE")
     add_bel_input(bel, wire_names[(x, y1, "ram/RE")], "RE")
 
-def add_bel_gb(x, y, g):
+def add_bel_gb(xy, x, y, g):
+    if xy[0] != x or xy[1] != y:
+        return
+
     bel = len(bel_name)
     bel_name.append("X%d/Y%d/gb" % (x, y))
     bel_type.append("SB_GB")
-    bel_pos.append((x, y, 0))
+    bel_pos.append((x, y, 2))
     bel_wires.append(list())
 
     add_bel_input(bel, wire_names[(x, y, "fabout")], "USER_SIGNAL_TO_GLOBAL_BUFFER")
@@ -605,51 +612,58 @@ for tile_xy, tile_type in sorted(tiles.items()):
     if tile_type == "logic":
         for i in range(8):
             add_bel_lc(tile_xy[0], tile_xy[1], i)
+
     if tile_type == "io":
         for i in range(2):
             add_bel_io(tile_xy[0], tile_xy[1], i)
+
+        if dev_name == "1k":
+            add_bel_gb(tile_xy,  7,  0, 0)
+            add_bel_gb(tile_xy,  7, 17, 1)
+            add_bel_gb(tile_xy, 13,  9, 2)
+            add_bel_gb(tile_xy,  0,  9, 3)
+            add_bel_gb(tile_xy,  6, 17, 4)
+            add_bel_gb(tile_xy,  6,  0, 5)
+            add_bel_gb(tile_xy,  0,  8, 6)
+            add_bel_gb(tile_xy, 13,  8, 7)
+        elif dev_name == "5k":
+            add_bel_gb(tile_xy, 13,  0, 0)
+            add_bel_gb(tile_xy, 13, 31, 1)
+            add_bel_gb(tile_xy, 19, 31, 2)
+            add_bel_gb(tile_xy,  6, 31, 3)
+            add_bel_gb(tile_xy, 12, 31, 4)
+            add_bel_gb(tile_xy, 12,  0, 5)
+            add_bel_gb(tile_xy,  6,  0, 6)
+            add_bel_gb(tile_xy, 19,  0, 7)
+        elif dev_name == "8k":
+            add_bel_gb(tile_xy, 33, 16,  7)
+            add_bel_gb(tile_xy,  0, 16,  6)
+            add_bel_gb(tile_xy, 17, 33,  1)
+            add_bel_gb(tile_xy, 17,  0,  0)
+            add_bel_gb(tile_xy,  0, 17,  3)
+            add_bel_gb(tile_xy, 33, 17,  2)
+            add_bel_gb(tile_xy, 16,  0,  5)
+            add_bel_gb(tile_xy, 16, 33,  4)
+        elif dev_name == "384":
+            add_bel_gb(tile_xy,  7,  4,  7)
+            add_bel_gb(tile_xy,  0,  4,  6)
+            add_bel_gb(tile_xy,  4,  9,  1)
+            add_bel_gb(tile_xy,  4,  0,  0)
+            add_bel_gb(tile_xy,  0,  5,  3)
+            add_bel_gb(tile_xy,  7,  5,  2)
+            add_bel_gb(tile_xy,  3,  0,  5)
+            add_bel_gb(tile_xy,  3,  9,  4)
+
     if tile_type == "ramb":
         add_bel_ram(tile_xy[0], tile_xy[1])
 
-if dev_name == "1k":
-    add_bel_gb( 7,  0, 0)
-    add_bel_gb( 7, 17, 1)
-    add_bel_gb(13,  9, 2)
-    add_bel_gb( 0,  9, 3)
-    add_bel_gb( 6, 17, 4)
-    add_bel_gb( 6,  0, 5)
-    add_bel_gb( 0,  8, 6)
-    add_bel_gb(13,  8, 7)
-elif dev_name == "5k":
-    add_bel_gb(13,  0, 0)
-    add_bel_gb(13, 31, 1)
-    add_bel_gb(19, 31, 2)
-    add_bel_gb( 6, 31, 3)
-    add_bel_gb(12, 31, 4)
-    add_bel_gb(12,  0, 5)
-    add_bel_gb( 6,  0, 6)
-    add_bel_gb(19,  0, 7)
-elif dev_name == "8k":
-    add_bel_gb(33, 16,  7)
-    add_bel_gb( 0, 16,  6)
-    add_bel_gb(17, 33,  1)
-    add_bel_gb(17,  0,  0)
-    add_bel_gb( 0, 17,  3)
-    add_bel_gb(33, 17,  2)
-    add_bel_gb(16,  0,  5)
-    add_bel_gb(16, 33,  4)
-elif dev_name == "384":
-    add_bel_gb( 7,  4,  7)
-    add_bel_gb( 0,  4,  6)
-    add_bel_gb( 4,  9,  1)
-    add_bel_gb( 4,  0,  0)
-    add_bel_gb( 0,  5,  3)
-    add_bel_gb( 7,  5,  2)
-    add_bel_gb( 3,  0,  5)
-    add_bel_gb( 3,  9,  4)
+    for ec in sorted(extra_cells.keys()):
+        if ec[1] == tile_xy[0] and ec[2] == tile_xy[1]:
+            add_bel_ec(ec)
 
 for ec in sorted(extra_cells.keys()):
-    add_bel_ec(ec)
+    if ec[1] == 0 and ec[2] == 0:
+        add_bel_ec(ec)
 
 class BinaryBlobAssembler:
     def __init__(self, cname, endianness, nodebug = False):
diff --git a/ice40/main.cc b/ice40/main.cc
index 24b49184..4de05d00 100644
--- a/ice40/main.cc
+++ b/ice40/main.cc
@@ -107,6 +107,7 @@ int main(int argc, char *argv[])
         options.add_options()("seed", po::value<int>(), "seed value for random number generator");
         options.add_options()("version,V", "show version");
         options.add_options()("tmfuzz", "run path delay estimate fuzzer");
+        options.add_options()("test", "check architecture database integrity");
 #ifdef ICE40_HX1K_ONLY
         options.add_options()("hx1k", "set device type to iCE40HX1K");
 #else
@@ -315,6 +316,9 @@ int main(int argc, char *argv[])
             std::cout << "</svg>\n";
         }
 
+        if (vm.count("test"))
+            ctx->archcheck();
+
         if (vm.count("tmfuzz")) {
             std::vector<WireId> src_wires, dst_wires;
 
@@ -360,8 +364,10 @@ int main(int argc, char *argv[])
                        ctx->chip_info->wire_data[dst.index].type);
             }
         }
+
         if (vm.count("freq"))
             ctx->target_freq = vm["freq"].as<double>() * 1e6;
+
         ctx->timing_driven = true;
         if (vm.count("no-tmdriv"))
             ctx->timing_driven = false;