Add Arch::getBelPinType() and Arch::getWireBelPins() in iCE40 arch

Signed-off-by: Clifford Wolf <clifford@clifford.at>

3 files changed, 57 insertions, 4 deletions

diff --git a/ice40/arch.cc b/ice40/arch.cc
index a670f286..5f0384a3 100644
--- a/ice40/arch.cc
+++ b/ice40/arch.cc
@@ -308,6 +308,20 @@ BelRange Arch::getBelsAtSameTile(BelId bel) const
     return br;
 }
 
+PortType Arch::getBelPinType(BelId bel, PortPin pin) const
+{
+    NPNR_ASSERT(bel != BelId());
+
+    int num_bel_wires = chip_info->bel_data[bel.index].num_bel_wires;
+    const BelWirePOD *bel_wires = chip_info->bel_data[bel.index].bel_wires.get();
+
+    for (int i = 0; i < num_bel_wires; i++)
+        if (bel_wires[i].port == pin)
+            return PortType(bel_wires[i].type);
+
+    return PORT_INOUT;
+}
+
 WireId Arch::getBelPinWire(BelId bel, PortPin pin) const
 {
     WireId ret;
diff --git a/ice40/arch.h b/ice40/arch.h
index 566f807a..f3016424 100644
--- a/ice40/arch.h
+++ b/ice40/arch.h
@@ -46,6 +46,7 @@ template <typename T> struct RelPtr
 NPNR_PACKED_STRUCT(struct BelWirePOD {
     int32_t wire_index;
     PortPin port;
+    int32_t type;
 });
 
 NPNR_PACKED_STRUCT(struct BelInfoPOD {
@@ -86,6 +87,9 @@ NPNR_PACKED_STRUCT(struct WireInfoPOD {
     BelPortPOD bel_uphill;
     RelPtr<BelPortPOD> bels_downhill;
 
+    int32_t num_bel_pins;
+    RelPtr<BelPortPOD> bel_pins;
+
     int32_t num_segments;
     RelPtr<WireSegmentPOD> segments;
 
@@ -466,8 +470,9 @@ struct Arch : BaseCtx
     }
 
     WireId getBelPinWire(BelId bel, PortPin pin) const;
+    PortType getBelPinType(BelId bel, PortPin pin) const;
 
-    BelPin getBelPinUphill(WireId wire) const
+    BelPin getBelPinUphill(WireId wire) const NPNR_DEPRECATED
     {
         BelPin ret;
         NPNR_ASSERT(wire != WireId());
@@ -480,7 +485,7 @@ struct Arch : BaseCtx
         return ret;
     }
 
-    BelPinRange getBelPinsDownhill(WireId wire) const
+    BelPinRange getBelPinsDownhill(WireId wire) const NPNR_DEPRECATED
     {
         BelPinRange range;
         NPNR_ASSERT(wire != WireId());
@@ -555,6 +560,15 @@ struct Arch : BaseCtx
         return delay;
     }
 
+    BelPinRange getWireBelPins(WireId wire) const
+    {
+        BelPinRange range;
+        NPNR_ASSERT(wire != WireId());
+        range.b.ptr = chip_info->wire_data[wire.index].bel_pins.get();
+        range.e.ptr = range.b.ptr + chip_info->wire_data[wire.index].num_bel_pins;
+        return range;
+    }
+
     WireRange getWires() const
     {
         WireRange range;
diff --git a/ice40/chipdb.py b/ice40/chipdb.py
index 329fef56..6e2bd2b5 100644
--- a/ice40/chipdb.py
+++ b/ice40/chipdb.py
@@ -43,6 +43,7 @@ packages = list()
 
 wire_uphill_belport = dict()
 wire_downhill_belports = dict()
+wire_belports = dict()
 
 wire_names = dict()
 wire_names_r = dict()
@@ -449,12 +450,18 @@ def add_bel_input(bel, wire, port):
     if wire not in wire_downhill_belports:
         wire_downhill_belports[wire] = set()
     wire_downhill_belports[wire].add((bel, port))
-    bel_wires[bel].append((wire, port))
+    if wire not in wire_belports:
+        wire_belports[wire] = set()
+    wire_belports[wire].add((bel, port))
+    bel_wires[bel].append((wire, port, 0))
 
 def add_bel_output(bel, wire, port):
     assert wire not in wire_uphill_belport
     wire_uphill_belport[wire] = (bel, port)
-    bel_wires[bel].append((wire, port))
+    if wire not in wire_belports:
+        wire_belports[wire] = set()
+    wire_belports[wire].add((bel, port))
+    bel_wires[bel].append((wire, port, 1))
 
 def add_bel_lc(x, y, z):
     bel = len(bel_name)
@@ -913,6 +920,7 @@ for bel in range(len(bel_name)):
     for i in range(len(bel_wires[bel])):
         bba.u32(bel_wires[bel][i][0], "wire_index")
         bba.u32(portpins[bel_wires[bel][i][1]], "port")
+        bba.u32(bel_wires[bel][i][2], "type")
         index += 1
 
 bba.l("bel_data_%s" % dev_name, "BelInfoPOD")
@@ -988,6 +996,15 @@ for wire in range(num_wires):
     else:
         num_bels_downhill = 0
 
+    if wire in wire_belports:
+        num_bel_pins = len(wire_belports[wire])
+        bba.l("wire%d_bels" % wire, "BelPortPOD")
+        for belport in sorted(wire_belports[wire]):
+            bba.u32(belport[0], "bel_index")
+            bba.u32(portpins[belport[1]], "port")
+    else:
+        num_bel_pins = 0
+
     info = dict()
     info["name"] = "X%d/Y%d/%s" % wire_names_r[wire]
 
@@ -1000,6 +1017,9 @@ for wire in range(num_wires):
     info["num_bels_downhill"] = num_bels_downhill
     info["list_bels_downhill"] = ("wire%d_downbels" % wire) if num_bels_downhill > 0 else None
 
+    info["num_bel_pins"] = num_bel_pins
+    info["list_bel_pins"] = ("wire%d_bels" % wire) if num_bel_pins > 0 else None
+
     if wire in wire_uphill_belport:
         info["uphill_bel"] = wire_uphill_belport[wire][0]
         info["uphill_pin"] = portpins[wire_uphill_belport[wire][1]]
@@ -1007,6 +1027,9 @@ for wire in range(num_wires):
         info["uphill_bel"] = -1
         info["uphill_pin"] = 0
 
+    if num_bels_downhill == 0:
+        info["list_bel_pins"] = None
+
     avg_x, avg_y = 0, 0
     if wire in wire_xy:
         for x, y in wire_xy[wire]:
@@ -1085,6 +1108,8 @@ for wire, info in enumerate(wireinfo):
     bba.u32(info["uphill_bel"], "bel_uphill.bel_index")
     bba.u32(info["uphill_pin"], "bel_uphill.port")
     bba.r(info["list_bels_downhill"], "bels_downhill")
+    bba.u32(info["num_bel_pins"], "num_bel_pins")
+    bba.r(info["list_bel_pins"], "bel_pins")
     bba.u32(len(wire_segments[wire]), "num_segments")
     if len(wire_segments[wire]):
         bba.r("wire_segments_%d" % wire, "segments")