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* Very slow SA placer based on arachne-pnrDavid Shah2018-06-161-60/+241
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Experimenting with more unplacingDavid Shah2018-06-161-6/+11
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Adding randomness and changes metrics to placerDavid Shah2018-06-161-9/+25
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Updating placerDavid Shah2018-06-161-7/+35
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Update basic placer to use new APIDavid Shah2018-06-161-4/+10
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Another heuristic experimentDavid Shah2018-06-161-77/+18
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Playing about with placement heuristicsDavid Shah2018-06-161-5/+19
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* experiment: Simple heuristic-based placerDavid Shah2018-06-163-3/+129
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Add output of estimated total wire delay to router (as metric for placement ↵Clifford Wolf2018-06-141-0/+49
| | | | | | quality) Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Increase ripup penalties over timeClifford Wolf2018-06-141-2/+8
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add route-ripup routing loopClifford Wolf2018-06-141-31/+175
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Refactor position/delay estimation APIClifford Wolf2018-06-141-16/+13
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* python: Clear SIGINT handler after Python loadsDavid Shah2018-06-141-0/+2
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Improve router error reportingClifford Wolf2018-06-131-4/+15
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Improve router error messagesClifford Wolf2018-06-131-5/+13
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add support for CellInfo->pins in routerClifford Wolf2018-06-131-3/+15
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix router error handling for unplaced cellsClifford Wolf2018-06-131-2/+5
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add A*-like optimizations to routerClifford Wolf2018-06-133-22/+69
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Remove IO buffers when fed by SB_IODavid Shah2018-06-131-9/+24
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* reveresed logic for enabling main file, and made tests link arch filesMiodrag Milanovic2018-06-121-2/+2
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* Fixing regression due to IDStringsDavid Shah2018-06-121-0/+7
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Minor clangformat changesClifford Wolf2018-06-122-4/+7
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnrClifford Wolf2018-06-122-1/+6
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| * Minimal Python bindings for IdStringDavid Shah2018-06-121-0/+5
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * ice40: Add support for LC placement constraints in packerDavid Shah2018-06-121-1/+1
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
* | Add fast IdString <-> PortPin conversionClifford Wolf2018-06-122-2/+12
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add proper fast IdStringClifford Wolf2018-06-122-12/+80
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add IdString APIClifford Wolf2018-06-123-11/+45
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnrClifford Wolf2018-06-122-1/+7
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| * Implement the placement validity checkerDavid Shah2018-06-121-1/+3
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * ice40: Start working on a packer, currently not testedDavid Shah2018-06-121-0/+4
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
* | Add nextpnr namespaceClifford Wolf2018-06-1215-34/+90
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* ice40: Adding cell utilities for packingDavid Shah2018-06-122-15/+27
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Adding some utilities for packingDavid Shah2018-06-122-0/+100
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Add "nextpnr.h"Clifford Wolf2018-06-119-55/+78
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Remove pool, dict, vector namespace aliasesClifford Wolf2018-06-113-17/+12
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Renamed LOC attribute to BEL, fix ice40 IO bel namesClifford Wolf2018-06-091-3/+3
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Adding basic placement constraintsDavid Shah2018-06-092-2/+40
| | | | | | | Specify the attribute (* LOC="bel_name" *) on any cell to constrain its placement to that bel. Signed-off-by: David Shah <davey1576@gmail.com>
* Add very basic routerClifford Wolf2018-06-093-3/+201
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Remove writing on sell types to cout (left over debug output?)Clifford Wolf2018-06-091-1/+0
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Improving the Python bindings, particularly the map/pair wrappersDavid Shah2018-06-082-6/+162
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* python: Fixing builds as importable moduleDavid Shah2018-06-081-0/+4
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Reformat remaining filesDavid Shah2018-06-083-87/+100
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Applied clang-format to my own contributionsZipCPU2018-06-075-255/+255
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* Adjusted info message names for rule-checker and parserZipCPU2018-06-071-1/+2
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* Fix placer build for dummy archClifford Wolf2018-06-071-3/+3
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Moved placer definitions to place.h, main automatically runs placer nowZipCPU2018-06-072-3/+27
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* Initial (random) placer capabilityZipCPU2018-06-072-5/+92
| | | | | | | | | | This commit also includes changes to jsonparse to allow it to 1) recognize ports with no connection, and set their net pointers to NULL 2) recognize designs with a ports node rather than a ports_direction The rule checker has also been modified to accommodate possible NULL netlists The ice40 chip now also has iterator operations ++bi and bi++.
* Merge branch 'master' into gqtechZipCPU2018-06-076-127/+367
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| * Replacing Boost type_traits with stdDavid Shah2018-06-071-1/+1
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
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