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author | Clifford Wolf <clifford@clifford.at> | 2018-06-13 17:52:18 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2018-06-13 17:52:18 +0200 |
commit | 794fc6df607d76cd3763dea75f7c93ad48aa306f (patch) | |
tree | 7dc9abb8dce28d18b3f6a5c439b2136cca9bdbfa /common | |
parent | 1a3d0f2f5dd763e08a237d53e92d775704f46f01 (diff) | |
download | nextpnr-794fc6df607d76cd3763dea75f7c93ad48aa306f.tar.gz nextpnr-794fc6df607d76cd3763dea75f7c93ad48aa306f.tar.bz2 nextpnr-794fc6df607d76cd3763dea75f7c93ad48aa306f.zip |
Add support for CellInfo->pins in router
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'common')
-rw-r--r-- | common/route.cc | 18 |
1 files changed, 15 insertions, 3 deletions
diff --git a/common/route.cc b/common/route.cc index e9fe2204..79bf13b0 100644 --- a/common/route.cc +++ b/common/route.cc @@ -77,8 +77,13 @@ void route_design(Design *design, bool verbose) auto src_pos = chip.getBelPosition(src_bel); - auto src_wire = chip.getWireBelPin( - src_bel, portPinFromId(net_info->driver.port)); + IdString driver_port = net_info->driver.port; + + auto driver_port_it = net_info->driver.cell->pins.find(driver_port); + if (driver_port_it != net_info->driver.cell->pins.end()) + driver_port = driver_port_it->second; + + auto src_wire = chip.getWireBelPin(src_bel, portPinFromId(driver_port)); if (src_wire == WireId()) log_error("No wire found for port %s on source bel.\n", @@ -110,8 +115,15 @@ void route_design(Design *design, bool verbose) chip.estimateDelay(src_pos, dst_pos)); } + IdString user_port = user_it.port; + + auto user_port_it = user_it.cell->pins.find(user_port); + + if (user_port_it != user_it.cell->pins.end()) + user_port = user_port_it->second; + auto dst_wire = - chip.getWireBelPin(dst_bel, portPinFromId(user_it.port)); + chip.getWireBelPin(dst_bel, portPinFromId(user_port)); if (dst_wire == WireId()) log_error("No wire found for port %s on destination bel.\n", |