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* cmake: Make HeAP placer always-enabledgatecat2023-03-171-21/+0
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* router1: Add error when dest port has no wiregatecat2023-03-061-0/+4
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* common: disable parallel refinement only without threads.Catherine2023-02-235-9/+9
| | | | Previously it was always disabled on WebAssembly builds.
* common: update deprecated use of `boost::filesystem::basename`.Catherine2023-02-231-2/+2
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* common: add missing includes for libc++.Catherine2023-02-232-0/+3
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* Include <cstdint> in common/kernel/hashlib.hThomas W Rodgers2023-02-181-0/+1
| | | | | | | The definitions for uint32_t, uint64_t report as undefined when compiling under GCC13. They were previously found by transitive includes, but this is not guaranteed to work, and GCC13 forced the issue.
* common: Print out generated seed valuerowanG0772023-02-161-1/+3
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* common: Implement Werror flagrowanG0772023-02-133-9/+29
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* clangformatgatecat2023-01-251-1/+4
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Add missing <set> includesgatecat2023-01-202-0/+3
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* context: Add getNetinfoRouteDelayQuadgatecat2023-01-183-1/+49
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* clangformatgatecat2023-01-022-4/+8
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* initialize netShareWeightMiodrag Milanovic2022-12-221-0/+1
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* propagate netShareWeightMiodrag Milanovic2022-12-222-1/+6
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* Remove deprecated functionsMiodrag Milanovic2022-12-223-26/+4
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* Merge pull request #1066 from arjenroodselaar/place_timeoutmyrtle2022-12-213-6/+26
|\ | | | | Timeout when legal placement can't be found for cell
| * Set divisor instead of absolute valueArjen Roodselaar2022-12-202-5/+10
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| * Allow setting cell placement timeoutArjen Roodselaar2022-12-203-13/+16
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| * Add --no-placer-timeout flag to override timeout during refinementArjen Roodselaar2022-12-193-5/+12
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| * Increase timeoutArjen Roodselaar2022-12-191-2/+4
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| * Timeout when legal placement can't be found for cellArjen Roodselaar2022-12-171-3/+6
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* | heap: encourage more spreading of heterogenous chainsgatecat2022-12-171-2/+2
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* api: add explain_invalid option to isBelLocationValidgatecat2022-12-075-8/+8
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* heap: Remove custom bounding-box typegatecat2022-12-071-6/+0
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* refactor: ArcBounds -> BoundingBoxgatecat2022-12-074-23/+23
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* api: Make NetInfo* of checkPipAvailForNet constgatecat2022-12-022-2/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Fix "implicit copy constructor for 'Property' is deprecated"gatecat2022-11-101-0/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* run clangformatgatecat2022-10-171-6/+10
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Modify code to meet the code style preferencesairskywater2022-09-241-4/+4
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* Add more sanity check for pointersairskywater2022-09-241-0/+1
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* fix runtime segmentation faultairskywater2022-09-241-0/+5
| | | disable null pointer dereference!
* Merge pull request #1019 from antmicro/support-clock-relationsmyrtle2022-09-203-7/+289
|\ | | | | Support cross-domain clock relations in timing analyser
| * Added the --ignore-rel-clk option to control timing checks for cross-domain ↵Maciej Kurc2022-09-203-115/+108
| | | | | | | | | | | | paths, formatted code Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * Code cleanupMaciej Kurc2022-08-311-64/+35
| | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * Added timing check for cross-domain paths for related clocksMaciej Kurc2022-08-311-4/+104
| | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * Augmented TimingAnalyser class with detection of clock to clock relationsMaciej Kurc2022-08-302-7/+225
| | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* | router2: Reserve source wire, toogatecat2022-09-201-0/+7
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* add missing overridesMiodrag Milanovic2022-08-221-3/+3
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* Fix parameter orderMiodrag Milanovic2022-08-221-2/+1
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* pybindings: Mark CellInfo::bel as readonlygatecat2022-08-181-2/+1
| | | | | | | | bel bindings should be updated with bindBel/unbindBel during placement, or setting the BEL attribute for constraints before placement. Fixes #522 Signed-off-by: gatecat <gatecat@ds0.me>
* refactor: id(stringf(...)) to new idf(...) helpergatecat2022-08-103-4/+18
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* netlist: Add PseudoCell APIgatecat2022-07-0813-44/+179
| | | | | | | | | | | | | | | When implementing concepts such as partition pins or deliberately split nets, there's a need for something that looks like a cell (starts/ends routing with pins on nets, has timing data) but isn't mapped to a fixed bel in the architecture, but instead can have pin mappings defined at runtime. The PseudoCell allows this by providing an alternate, virtual-function based API for such cells. When a cell has `pseudo_cell` used, instead of calling functions such as getBelPinWire, getBelLocation or getCellDelay in the Arch API; such data is provided by the cell itself, fully flexible at runtime regardless of arch, via methods on the PseudoCell implementation.
* generic: Use arch_pybindings_sharedgatecat2022-07-041-0/+6
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Don't assert on mixed domain paths in reportgatecat2022-05-221-5/+0
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* common: Correct a minor typo in the messageYRabbit2022-05-101-1/+1
| | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* prefine: Do full-tile swaps, toogatecat2022-04-192-1/+100
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Move general parallel detail place code out of parallel_refinegatecat2022-04-175-545/+730
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Split up common into kernel,place,routegatecat2022-04-0874-0/+0
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* parallel_refine: Fix compile error with some configsgatecat2022-03-191-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* BUGFIX: disable the thousands separatorYRabbit2022-03-161-1/+8
| | | | | | | The wire numbers are very large and it is undesirable to use a thousand separator there. This is a side effect of enabling locale. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-14 00:58:19 +0000