Remove pool, dict, vector namespace aliases

Signed-off-by: Clifford Wolf <clifford@clifford.at>

3 files changed, 12 insertions, 17 deletions

diff --git a/common/design.h b/common/design.h
index 1591e0f2..d05e6095 100644
--- a/common/design.h
+++ b/common/design.h
@@ -30,11 +30,6 @@
 // replace with proper IdString later
 typedef std::string IdString;
 
-// replace with haslib later
-template <typename T> using pool = std::unordered_set<T>;
-template <typename T, typename U> using dict = std::unordered_map<T, U>;
-using std::vector;
-
 struct GraphicElement
 {
     // This will control colour, and there should be separate
@@ -82,11 +77,11 @@ struct NetInfo
 {
     IdString name;
     PortRef driver;
-    vector<PortRef> users;
-    dict<IdString, std::string> attrs;
+    std::vector<PortRef> users;
+    std::unordered_map<IdString, std::string> attrs;
 
     // wire -> uphill_pip
-    dict<WireId, PipId> wires;
+    std::unordered_map<WireId, PipId> wires;
 };
 
 enum PortType
@@ -106,12 +101,12 @@ struct PortInfo
 struct CellInfo
 {
     IdString name, type;
-    dict<IdString, PortInfo> ports;
-    dict<IdString, std::string> attrs, params;
+    std::unordered_map<IdString, PortInfo> ports;
+    std::unordered_map<IdString, std::string> attrs, params;
 
     BelId bel;
     // cell_port -> bel_pin
-    dict<IdString, IdString> pins;
+    std::unordered_map<IdString, IdString> pins;
 };
 
 struct Design
@@ -123,8 +118,8 @@ struct Design
         // ...
     }
 
-    dict<IdString, NetInfo *> nets;
-    dict<IdString, CellInfo *> cells;
+    std::unordered_map<IdString, NetInfo *> nets;
+    std::unordered_map<IdString, CellInfo *> cells;
 };
 
 #endif
diff --git a/common/pybindings.cc b/common/pybindings.cc
index 24269b55..82f35421 100644
--- a/common/pybindings.cc
+++ b/common/pybindings.cc
@@ -88,8 +88,8 @@ BOOST_PYTHON_MODULE(MODULE_NAME)
 
     WRAP_MAP(decltype(NetInfo::attrs), "IdStrMap");
 
-    class_<vector<PortRef>>("PortRefVector")
-            .def(vector_indexing_suite<vector<PortRef>>());
+    class_<std::vector<PortRef>>("PortRefVector")
+            .def(vector_indexing_suite<std::vector<PortRef>>());
 
     enum_<PortType>("PortType")
             .value("PORT_IN", PORT_IN)
diff --git a/common/route.cc b/common/route.cc
index b57bc29f..b98db259 100644
--- a/common/route.cc
+++ b/common/route.cc
@@ -71,7 +71,7 @@ void route_design(Design *design)
 
         log("    Source wire: %s\n", chip.getWireName(src_wire).c_str());
 
-        dict<WireId, DelayInfo> src_wires;
+        std::unordered_map<WireId, DelayInfo> src_wires;
         src_wires[src_wire] = DelayInfo();
         net_info->wires[src_wire] = PipId();
         chip.bindWire(src_wire, net_name);
@@ -97,7 +97,7 @@ void route_design(Design *design)
             log("    Destination wire: %s\n",
                 chip.getWireName(dst_wire).c_str());
 
-            dict<WireId, QueuedWire> visited;
+            std::unordered_map<WireId, QueuedWire> visited;
             std::priority_queue<QueuedWire, std::vector<QueuedWire>,
                                 std::greater<QueuedWire>>
                     queue;