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authorClifford Wolf <clifford@clifford.at>2018-11-09 12:57:14 +0100
committerClifford Wolf <clifford@clifford.at>2018-11-09 12:57:14 +0100
commit66dd17664c08aca17b53d2853558121aa9e702e4 (patch)
treeb6bc5dd919e5f525ec7328861b81f616673a1ea6 /ecp5
parente91241f10d68fcaaf0a81fa77e9a91666120ccee (diff)
parent15d9b3d3cc05656e58d01ba2f97ec92b6daaee1c (diff)
downloadnextpnr-66dd17664c08aca17b53d2853558121aa9e702e4.tar.gz
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Merge branch 'master' of github.com:YosysHQ/nextpnr into router_improve
Diffstat (limited to 'ecp5')
-rw-r--r--ecp5/arch.cc108
-rw-r--r--ecp5/arch.h35
-rw-r--r--ecp5/arch_place.cc38
-rw-r--r--ecp5/archdefs.h3
-rw-r--r--ecp5/bitstream.cc737
-rw-r--r--ecp5/cells.cc200
-rw-r--r--ecp5/cells.h7
-rw-r--r--ecp5/config.cc46
-rw-r--r--ecp5/config.h10
-rw-r--r--ecp5/constids.inc760
-rw-r--r--ecp5/globals.cc426
-rw-r--r--ecp5/globals.h27
-rw-r--r--ecp5/lpf.cc106
-rw-r--r--ecp5/main.cc34
-rw-r--r--ecp5/pack.cc566
-rwxr-xr-xecp5/trellis_import.py9
16 files changed, 3063 insertions, 49 deletions
diff --git a/ecp5/arch.cc b/ecp5/arch.cc
index 82ebfba1..4a0b31b5 100644
--- a/ecp5/arch.cc
+++ b/ecp5/arch.cc
@@ -19,13 +19,16 @@
*/
#include <algorithm>
+#include <boost/range/adaptor/reversed.hpp>
#include <cmath>
#include <cstring>
#include "gfx.h"
+#include "globals.h"
#include "log.h"
#include "nextpnr.h"
#include "placer1.h"
#include "router1.h"
+#include "timing.h"
#include "util.h"
NEXTPNR_NAMESPACE_BEGIN
@@ -74,11 +77,13 @@ Arch::Arch(ArchArgs args) : args(args)
log_error("Unsupported ECP5 chip type.\n");
}
#else
- if (args.type == ArchArgs::LFE5U_25F) {
+ if (args.type == ArchArgs::LFE5U_25F || args.type == ArchArgs::LFE5UM_25F || args.type == ArchArgs::LFE5UM5G_25F) {
chip_info = get_chip_info(reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_25k));
- } else if (args.type == ArchArgs::LFE5U_45F) {
+ } else if (args.type == ArchArgs::LFE5U_45F || args.type == ArchArgs::LFE5UM_45F ||
+ args.type == ArchArgs::LFE5UM5G_45F) {
chip_info = get_chip_info(reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_45k));
- } else if (args.type == ArchArgs::LFE5U_85F) {
+ } else if (args.type == ArchArgs::LFE5U_85F || args.type == ArchArgs::LFE5UM_85F ||
+ args.type == ArchArgs::LFE5UM5G_85F) {
chip_info = get_chip_info(reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_85k));
} else {
log_error("Unsupported ECP5 chip type.\n");
@@ -108,6 +113,18 @@ std::string Arch::getChipName() const
return "LFE5U-45F";
} else if (args.type == ArchArgs::LFE5U_85F) {
return "LFE5U-85F";
+ } else if (args.type == ArchArgs::LFE5UM_25F) {
+ return "LFE5UM-25F";
+ } else if (args.type == ArchArgs::LFE5UM_45F) {
+ return "LFE5UM-45F";
+ } else if (args.type == ArchArgs::LFE5UM_85F) {
+ return "LFE5UM-85F";
+ } else if (args.type == ArchArgs::LFE5UM5G_25F) {
+ return "LFE5UM5G-25F";
+ } else if (args.type == ArchArgs::LFE5UM5G_45F) {
+ return "LFE5UM5G-45F";
+ } else if (args.type == ArchArgs::LFE5UM5G_85F) {
+ return "LFE5UM5G-85F";
} else {
log_error("Unknown chip\n");
}
@@ -123,6 +140,18 @@ IdString Arch::archArgsToId(ArchArgs args) const
return id("lfe5u_45f");
if (args.type == ArchArgs::LFE5U_85F)
return id("lfe5u_85f");
+ if (args.type == ArchArgs::LFE5UM_25F)
+ return id("lfe5um_25f");
+ if (args.type == ArchArgs::LFE5UM_45F)
+ return id("lfe5um_45f");
+ if (args.type == ArchArgs::LFE5UM_85F)
+ return id("lfe5um_85f");
+ if (args.type == ArchArgs::LFE5UM5G_25F)
+ return id("lfe5um5g_25f");
+ if (args.type == ArchArgs::LFE5UM5G_45F)
+ return id("lfe5um5g_45f");
+ if (args.type == ArchArgs::LFE5UM5G_85F)
+ return id("lfe5um5g_85f");
return IdString();
}
@@ -389,7 +418,12 @@ bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay
bool Arch::place() { return placer1(getCtx(), Placer1Cfg(getCtx())); }
-bool Arch::route() { return router1(getCtx(), Router1Cfg(getCtx())); }
+bool Arch::route()
+{
+ route_ecp5_globals(getCtx());
+ assign_budget(getCtx(), true);
+ return router1(getCtx(), Router1Cfg(getCtx()));
+}
// -----------------------------------------------------------------------
@@ -504,12 +538,12 @@ bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort
delay.delay = 193;
return true;
}
-
+#if 0 // FIXME
if (fromPort == id_WCK && (toPort == id_F0 || toPort == id_F1)) {
delay.delay = 717;
return true;
}
-
+#endif
if ((fromPort == id_A0 && toPort == id_WADO3) || (fromPort == id_A1 && toPort == id_WDO1) ||
(fromPort == id_B0 && toPort == id_WADO1) || (fromPort == id_B1 && toPort == id_WDO3) ||
(fromPort == id_C0 && toPort == id_WADO2) || (fromPort == id_C1 && toPort == id_WDO0) ||
@@ -518,6 +552,25 @@ bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort
return true;
}
return false;
+ } else if (cell->type == id_DCCA) {
+ if (fromPort == id_CLKI && toPort == id_CLKO) {
+ delay.delay = 0;
+ return true;
+ }
+ return false;
+ } else if (cell->type == id_DP16KD) {
+ if (fromPort == id_CLKA) {
+ if (toPort.str(this).substr(0, 3) == "DOA") {
+ delay.delay = 4260;
+ return true;
+ }
+ } else if (fromPort == id_CLKB) {
+ if (toPort.str(this).substr(0, 3) == "DOB") {
+ delay.delay = 4280;
+ return true;
+ }
+ }
+ return false;
} else {
return false;
}
@@ -525,6 +578,8 @@ bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort
TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, IdString &clockPort) const
{
+ auto disconnected = [cell](IdString p) { return !cell->ports.count(p) || cell->ports.at(p).net == nullptr; };
+
if (cell->type == id_TRELLIS_SLICE) {
int sd0 = int_or_default(cell->params, id("REG0_SD"), 0), sd1 = int_or_default(cell->params, id("REG1_SD"), 0);
if (port == id_CLK || port == id_WCK)
@@ -532,6 +587,13 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, Id
if (port == id_A0 || port == id_A1 || port == id_B0 || port == id_B1 || port == id_C0 || port == id_C1 ||
port == id_D0 || port == id_D1 || port == id_FCI || port == id_FXA || port == id_FXB)
return TMG_COMB_INPUT;
+ if (port == id_F0 && disconnected(id_A0) && disconnected(id_B0) && disconnected(id_C0) && disconnected(id_D0) &&
+ disconnected(id_FCI))
+ return TMG_IGNORE; // LUT with no inputs is a constant
+ if (port == id_F1 && disconnected(id_A1) && disconnected(id_B1) && disconnected(id_C1) && disconnected(id_D1) &&
+ disconnected(id_FCI))
+ return TMG_IGNORE; // LUT with no inputs is a constant
+
if (port == id_F0 || port == id_F1 || port == id_FCO || port == id_OFX0 || port == id_OFX1)
return TMG_COMB_OUTPUT;
if (port == id_DI0 || port == id_DI1 || port == id_CE || port == id_LSR || (sd0 == 1 && port == id_M0) ||
@@ -563,6 +625,34 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, Id
if (port == id_O)
return TMG_STARTPOINT;
return TMG_IGNORE;
+ } else if (cell->type == id_DCCA) {
+ if (port == id_CLKI)
+ return TMG_COMB_INPUT;
+ if (port == id_CLKO)
+ return TMG_COMB_OUTPUT;
+ return TMG_IGNORE;
+ } else if (cell->type == id_DP16KD) {
+ if (port == id_CLKA || port == id_CLKB)
+ return TMG_CLOCK_INPUT;
+ std::string port_name = port.str(this);
+ for (auto c : boost::adaptors::reverse(port_name)) {
+ if (std::isdigit(c))
+ continue;
+ if (c == 'A')
+ clockPort = id_CLKA;
+ else if (c == 'B')
+ clockPort = id_CLKB;
+ else
+ NPNR_ASSERT_FALSE_STR("bad ram port");
+ return (cell->ports.at(port).type == PORT_OUT) ? TMG_REGISTER_OUTPUT : TMG_REGISTER_INPUT;
+ }
+ NPNR_ASSERT_FALSE_STR("no timing type for RAM port '" + port.str(this) + "'");
+ } else if (cell->type == id_MULT18X18D) {
+ return TMG_IGNORE; // FIXME
+ } else if (cell->type == id_ALU54B) {
+ return TMG_IGNORE; // FIXME
+ } else if (cell->type == id_EHXPLLL) {
+ return TMG_IGNORE;
} else {
NPNR_ASSERT_FALSE_STR("no timing data for cell type '" + cell->type.str(this) + "'");
}
@@ -579,4 +669,10 @@ std::vector<std::pair<std::string, std::string>> Arch::getTilesAtLocation(int ro
return ret;
}
+GlobalInfoPOD Arch::globalInfoAtLoc(Location loc)
+{
+ int locidx = loc.y * chip_info->width + loc.x;
+ return chip_info->location_glbinfo[locidx];
+}
+
NEXTPNR_NAMESPACE_END
diff --git a/ecp5/arch.h b/ecp5/arch.h
index da86d4e2..583d539f 100644
--- a/ecp5/arch.h
+++ b/ecp5/arch.h
@@ -147,6 +147,8 @@ NPNR_PACKED_STRUCT(struct GlobalInfoPOD {
int16_t tap_col;
TapDirection tap_dir;
GlobalQuadrant quad;
+ int16_t spine_row;
+ int16_t spine_col;
});
NPNR_PACKED_STRUCT(struct ChipInfoPOD {
@@ -390,6 +392,12 @@ struct ArchArgs
LFE5U_25F,
LFE5U_45F,
LFE5U_85F,
+ LFE5UM_25F,
+ LFE5UM_45F,
+ LFE5UM_85F,
+ LFE5UM5G_25F,
+ LFE5UM5G_45F,
+ LFE5UM5G_85F,
} type = NONE;
std::string package;
int speed = 6;
@@ -483,7 +491,7 @@ struct Arch : BaseCtx
BelId getBelByLocation(Loc loc) const;
BelRange getBelsByTile(int x, int y) const;
- bool getBelGlobalBuf(BelId bel) const { return false; }
+ bool getBelGlobalBuf(BelId bel) const { return getBelType(bel) == id_DCCA; }
bool checkBelAvail(BelId bel) const
{
@@ -640,6 +648,21 @@ struct Arch : BaseCtx
return range;
}
+ IdString getWireBasename(WireId wire) const { return id(locInfo(wire)->wire_data[wire.index].name.get()); }
+
+ WireId getWireByLocAndBasename(Location loc, std::string basename) const
+ {
+ WireId wireId;
+ wireId.location = loc;
+ for (int i = 0; i < locInfo(wireId)->num_wires; i++) {
+ if (locInfo(wireId)->wire_data[i].name.get() == basename) {
+ wireId.index = i;
+ return wireId;
+ }
+ }
+ return WireId();
+ }
+
// -------------------------------------------------
PipId getPipByName(IdString name) const;
@@ -891,6 +914,16 @@ struct Arch : BaseCtx
}
NPNR_ASSERT_FALSE_STR("no tile at (" + std::to_string(col) + ", " + std::to_string(row) + ") with type in set");
}
+
+ GlobalInfoPOD globalInfoAtLoc(Location loc);
+
+ // Apply LPF constraints to the context
+ bool applyLPF(std::string filename, std::istream &in);
+
+ IdString id_trellis_slice;
+ IdString id_clk, id_lsr;
+ IdString id_clkmux, id_lsrmux;
+ IdString id_srmode, id_mode;
};
NEXTPNR_NAMESPACE_END
diff --git a/ecp5/arch_place.cc b/ecp5/arch_place.cc
index 55fff73d..6fcd8bde 100644
--- a/ecp5/arch_place.cc
+++ b/ecp5/arch_place.cc
@@ -39,25 +39,27 @@ bool Arch::slicesCompatible(const std::vector<const CellInfo *> &cells) const
IdString CLKMUX, LSRMUX, SRMODE;
bool first = true;
for (auto cell : cells) {
- if (first) {
- clk_sig = cell->sliceInfo.clk_sig;
- lsr_sig = cell->sliceInfo.lsr_sig;
- CLKMUX = cell->sliceInfo.clkmux;
- LSRMUX = cell->sliceInfo.lsrmux;
- SRMODE = cell->sliceInfo.srmode;
- } else {
- if (cell->sliceInfo.clk_sig != clk_sig)
- return false;
- if (cell->sliceInfo.lsr_sig != lsr_sig)
- return false;
- if (cell->sliceInfo.clkmux != CLKMUX)
- return false;
- if (cell->sliceInfo.lsrmux != LSRMUX)
- return false;
- if (cell->sliceInfo.srmode != SRMODE)
- return false;
+ if (cell->sliceInfo.using_dff) {
+ if (first) {
+ clk_sig = cell->sliceInfo.clk_sig;
+ lsr_sig = cell->sliceInfo.lsr_sig;
+ CLKMUX = cell->sliceInfo.clkmux;
+ LSRMUX = cell->sliceInfo.lsrmux;
+ SRMODE = cell->sliceInfo.srmode;
+ } else {
+ if (cell->sliceInfo.clk_sig != clk_sig)
+ return false;
+ if (cell->sliceInfo.lsr_sig != lsr_sig)
+ return false;
+ if (cell->sliceInfo.clkmux != CLKMUX)
+ return false;
+ if (cell->sliceInfo.lsrmux != LSRMUX)
+ return false;
+ if (cell->sliceInfo.srmode != SRMODE)
+ return false;
+ }
+ first = false;
}
- first = false;
}
return true;
}
diff --git a/ecp5/archdefs.h b/ecp5/archdefs.h
index c4e1413f..b85852c2 100644
--- a/ecp5/archdefs.h
+++ b/ecp5/archdefs.h
@@ -136,11 +136,14 @@ struct DecalId
struct ArchNetInfo
{
+ bool is_global = false;
};
+
struct ArchCellInfo
{
struct
{
+ bool using_dff;
IdString clk_sig, lsr_sig, clkmux, lsrmux, srmode;
} sliceInfo;
};
diff --git a/ecp5/bitstream.cc b/ecp5/bitstream.cc
index a1edf9e5..95256732 100644
--- a/ecp5/bitstream.cc
+++ b/ecp5/bitstream.cc
@@ -20,6 +20,9 @@
#include "bitstream.h"
#include <fstream>
+#include <iomanip>
+#include <queue>
+#include <regex>
#include <streambuf>
#include "config.h"
@@ -61,6 +64,107 @@ static std::vector<bool> int_to_bitvector(int val, int size)
return bv;
}
+static std::vector<bool> str_to_bitvector(std::string str, int size)
+{
+ std::vector<bool> bv;
+ bv.resize(size, 0);
+ if (str.substr(0, 2) != "0b")
+ log_error("error parsing value '%s', expected 0b prefix\n", str.c_str());
+ for (int i = 0; i < int(str.size()) - 2; i++) {
+ char c = str.at((str.size() - i) - 1);
+ NPNR_ASSERT(c == '0' || c == '1');
+ bv.at(i) = (c == '1');
+ }
+ return bv;
+}
+
+// Tie a wire using the CIB ties
+static void tie_cib_signal(Context *ctx, ChipConfig &cc, WireId wire, bool value)
+{
+ static const std::regex cib_re("J([A-D]|CE|LSR|CLK)[0-7]");
+ std::queue<WireId> signals;
+ signals.push(wire);
+ WireId cibsig;
+ std::string basename;
+ while (true) {
+ NPNR_ASSERT(!signals.empty());
+ NPNR_ASSERT(signals.size() < 100);
+ cibsig = signals.front();
+ basename = ctx->getWireBasename(cibsig).str(ctx);
+ signals.pop();
+ if (std::regex_match(basename, cib_re))
+ break;
+ for (auto pip : ctx->getPipsUphill(cibsig))
+ signals.push(ctx->getPipSrcWire(pip));
+ }
+
+ bool out_value = value;
+ if (basename.substr(0, 3) == "JCE")
+ NPNR_ASSERT(value);
+ if (basename.substr(0, 4) == "JCLK" || basename.substr(0, 4) == "JLSR") {
+ NPNR_ASSERT(value);
+ out_value = 0;
+ }
+
+ for (const auto &tile : ctx->getTilesAtLocation(cibsig.location.y, cibsig.location.x)) {
+ if (tile.second.substr(0, 3) == "CIB" || tile.second.substr(0, 4) == "VCIB") {
+
+ cc.tiles[tile.first].add_enum("CIB." + basename + "MUX", out_value ? "1" : "0");
+ return;
+ }
+ }
+ NPNR_ASSERT_FALSE("CIB tile not found at location");
+}
+
+inline int chtohex(char c)
+{
+ static const std::string hex = "0123456789ABCDEF";
+ return hex.find(c);
+}
+
+std::vector<bool> parse_init_str(const std::string &str, int length)
+{
+ // Parse a string that may be binary or hex
+ std::vector<bool> result;
+ result.resize(length, false);
+ if (str.substr(0, 2) == "0x") {
+ // Lattice style hex string
+ if (int(str.length()) > (2 + ((length + 3) / 4)))
+ log_error("hex string value too long, expected up to %d chars and found %d.\n", (2 + ((length + 3) / 4)),
+ int(str.length()));
+ for (int i = 0; i < int(str.length()) - 2; i++) {
+ char c = str.at((str.size() - i) - 1);
+ int nibble = chtohex(c);
+ result.at(i * 4) = nibble & 0x1;
+ if (i * 4 + 1 < length)
+ result.at(i * 4 + 1) = nibble & 0x2;
+ if (i * 4 + 2 < length)
+ result.at(i * 4 + 2) = nibble & 0x4;
+ if (i * 4 + 3 < length)
+ result.at(i * 4 + 3) = nibble & 0x8;
+ }
+ } else {
+ // Yosys style binary string
+ if (int(str.length()) > length)
+ log_error("hex string value too long, expected up to %d bits and found %d.\n", length, int(str.length()));
+ for (int i = 0; i < int(str.length()); i++) {
+ char c = str.at((str.size() - i) - 1);
+ NPNR_ASSERT(c == '0' || c == '1' || c == 'X' || c == 'x');
+ result.at(i) = (c == '1');
+ }
+ }
+ return result;
+}
+
+inline uint16_t bit_reverse(uint16_t x, int size)
+{
+ uint16_t y = 0;
+ for (int i = 0; i < size; i++)
+ if (x & (1 << i))
+ y |= (1 << ((size - 1) - i));
+ return y;
+}
+
// Get the PIO tile corresponding to a PIO bel
static std::string get_pio_tile(Context *ctx, BelId bel)
{
@@ -144,6 +248,221 @@ static std::string get_pic_tile(Context *ctx, BelId bel)
}
}
+// Get the list of tiles corresponding to a blockram
+std::vector<std::string> get_bram_tiles(Context *ctx, BelId bel)
+{
+ std::vector<std::string> tiles;
+ Loc loc = ctx->getBelLocation(bel);
+
+ static const std::set<std::string> ebr0 = {"MIB_EBR0", "EBR_CMUX_UR", "EBR_CMUX_LR", "EBR_CMUX_LR_25K"};
+ static const std::set<std::string> ebr8 = {"MIB_EBR8", "EBR_SPINE_UL1", "EBR_SPINE_UR1", "EBR_SPINE_LL1",
+ "EBR_CMUX_UL", "EBR_SPINE_LL0", "EBR_CMUX_LL", "EBR_SPINE_LR0",
+ "EBR_SPINE_LR1", "EBR_CMUX_LL_25K", "EBR_SPINE_UL2", "EBR_SPINE_UL0",
+ "EBR_SPINE_UR2", "EBR_SPINE_LL2", "EBR_SPINE_LR2", "EBR_SPINE_UR0"};
+
+ switch (loc.z) {
+ case 0:
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x, ebr0));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 1, "MIB_EBR1"));
+ break;
+ case 1:
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x, "MIB_EBR2"));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 1, "MIB_EBR3"));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 2, "MIB_EBR4"));
+ break;
+ case 2:
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x, "MIB_EBR4"));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 1, "MIB_EBR5"));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 2, "MIB_EBR6"));
+ break;
+ case 3:
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x, "MIB_EBR6"));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 1, "MIB_EBR7"));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 2, ebr8));
+ break;
+ default:
+ NPNR_ASSERT_FALSE("bad EBR z loc");
+ }
+ return tiles;
+}
+
+// Get the list of tiles corresponding to a DSP
+std::vector<std::string> get_dsp_tiles(Context *ctx, BelId bel)
+{
+ std::vector<std::string> tiles;
+ Loc loc = ctx->getBelLocation(bel);
+
+ static const std::set<std::string> dsp8 = {"MIB_DSP8", "DSP_SPINE_UL0", "DSP_SPINE_UR0", "DSP_SPINE_UR1"};
+ if (ctx->getBelType(bel) == id_MULT18X18D) {
+ switch (loc.z) {
+ case 0:
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x, "MIB_DSP0"));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x, "MIB2_DSP0"));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 1, "MIB_DSP1"));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 1, "MIB2_DSP1"));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 2, "MIB_DSP2"));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 2, "MIB2_DSP2"));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 3, "MIB_DSP3"));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 3, "MIB2_DSP3"));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 4, "MIB_DSP4"));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 4, "MIB2_DSP4"));
+ break;
+ case 1:
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x - 1, "MIB_DSP0"));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x - 1, "MIB2_DSP0"));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x, "MIB_DSP1"));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x, "MIB2_DSP1"));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 1, "MIB_DSP2"));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 1, "MIB2_DSP2"));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 2, "MIB_DSP3"));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 2, "MIB2_DSP3"));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 3, "MIB_DSP4"));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 3, "MIB2_DSP4"));
+ break;
+ case 4:
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x, "MIB_DSP4"));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x, "MIB2_DSP4"));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 1, "MIB_DSP5"));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 1, "MIB2_DSP5"));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 2, "MIB_DSP6"));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 2, "MIB2_DSP6"));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 3, "MIB_DSP7"));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 3, "MIB2_DSP7"));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 4, dsp8));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 4, "MIB2_DSP8"));
+ break;
+ case 5:
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x - 1, "MIB_DSP4"));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x - 1, "MIB2_DSP4"));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x, "MIB_DSP5"));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x, "MIB2_DSP5"));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 1, "MIB_DSP6"));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 1, "MIB2_DSP6"));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 2, "MIB_DSP7"));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 2, "MIB2_DSP7"));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 3, dsp8));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 3, "MIB2_DSP8"));
+ break;
+ default:
+ NPNR_ASSERT_FALSE("bad MULT z loc");
+ }
+ } else if (ctx->getBelType(bel) == id_ALU54B) {
+ switch (loc.z) {
+ case 3:
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x - 3, "MIB_DSP0"));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x - 3, "MIB2_DSP0"));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x - 2, "MIB_DSP1"));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x - 2, "MIB2_DSP1"));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x - 1, "MIB_DSP2"));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x - 1, "MIB2_DSP2"));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x, "MIB_DSP3"));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x, "MIB2_DSP3"));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 1, "MIB_DSP4"));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 1, "MIB2_DSP4"));
+ break;
+ case 7:
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x - 3, "MIB_DSP4"));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x - 3, "MIB2_DSP4"));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x - 2, "MIB_DSP5"));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x - 2, "MIB2_DSP5"));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x - 1, "MIB_DSP6"));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x - 1, "MIB2_DSP6"));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x, "MIB_DSP7"));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x, "MIB2_DSP7"));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 1, dsp8));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 1, "MIB2_DSP8"));
+ break;
+ default:
+ NPNR_ASSERT_FALSE("bad ALU z loc");
+ }
+ }
+ return tiles;
+}
+
+// Get the list of tiles corresponding to a PLL
+std::vector<std::string> get_pll_tiles(Context *ctx, BelId bel)
+{
+ std::string name = ctx->locInfo(bel)->bel_data[bel.index].name.get();
+ std::vector<std::string> tiles;
+ Loc loc = ctx->getBelLocation(bel);
+
+ if (name == "EHXPLL_UL") {
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x - 1, "PLL0_UL"));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y + 1, loc.x - 1, "PLL1_UL"));
+ } else if (name == "EHXPLL_LL") {
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y + 1, loc.x, "PLL0_LL"));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y + 1, loc.x + 1, "BANKREF8"));
+ } else if (name == "EHXPLL_LR") {
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y + 1, loc.x, "PLL0_LR"));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y + 1, loc.x - 1, "PLL1_LR"));
+ } else if (name == "EHXPLL_UR") {
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x - 1, "PLL0_UR"));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y + 1, loc.x - 1, "PLL1_UR"));
+ } else {
+ NPNR_ASSERT_FALSE_STR("bad PLL loc " + name);
+ }
+ return tiles;
+}
+
+void fix_tile_names(Context *ctx, ChipConfig &cc)
+{
+ // Remove the V prefix/suffix on certain tiles if device is a SERDES variant
+ if (ctx->args.type == ArchArgs::LFE5UM_25F || ctx->args.type == ArchArgs::LFE5UM_45F ||
+ ctx->args.type == ArchArgs::LFE5UM_85F || ctx->args.type == ArchArgs::LFE5UM5G_25F ||
+ ctx->args.type == ArchArgs::LFE5UM5G_45F || ctx->args.type == ArchArgs::LFE5UM5G_85F) {
+ std::map<std::string, std::string> tiletype_xform;
+ for (const auto &tile : cc.tiles) {
+ std::string newname = tile.first;
+ auto vcib = tile.first.find("VCIB");
+ if (vcib != std::string::npos) {
+ // Remove the V
+ newname.erase(vcib, 1);
+ tiletype_xform[tile.first] = newname;
+ } else if (tile.first.back() == 'V') {
+ // BMID_0V or BMID_2V
+ if (tile.first.at(tile.first.size() - 2) == '0') {
+ newname.at(tile.first.size() - 1) = 'H';
+ tiletype_xform[tile.first] = newname;
+ } else if (tile.first.at(tile.first.size() - 2) == '2') {
+ newname.pop_back();
+ tiletype_xform[tile.first] = newname;
+ }
+ }
+ }
+ // Apply the name changes
+ for (auto xform : tiletype_xform) {
+ cc.tiles[xform.second] = cc.tiles.at(xform.first);
+ cc.tiles.erase(xform.first);
+ }
+ }
+}
+
+void tieoff_dsp_ports(Context *ctx, ChipConfig &cc, CellInfo *ci)
+{
+ for (auto port : ci->ports) {
+ if (port.second.net == nullptr && port.second.type == PORT_IN) {
+ if (port.first.str(ctx).substr(0, 3) == "CLK" || port.first.str(ctx).substr(0, 2) == "CE" ||
+ port.first.str(ctx).substr(0, 3) == "RST" || port.first.str(ctx).substr(0, 3) == "SRO" ||
+ port.first.str(ctx).substr(0, 3) == "SRI" || port.first.str(ctx).substr(0, 2) == "RO" ||
+ port.first.str(ctx).substr(0, 2) == "MA" || port.first.str(ctx).substr(0, 2) == "MB" ||
+ port.first.str(ctx).substr(0, 3) == "CFB" || port.first.str(ctx).substr(0, 3) == "CIN" ||
+ port.first.str(ctx).substr(0, 6) == "SOURCE" || port.first.str(ctx).substr(0, 6) == "SIGNED" ||
+ port.first.str(ctx).substr(0, 2) == "OP")
+ continue;
+ bool value = bool_or_default(ci->params, ctx->id(port.first.str(ctx) + "MUX"), false);
+ tie_cib_signal(ctx, cc, ctx->getBelPinWire(ci->bel, port.first), value);
+ }
+ }
+}
+
+static void set_pip(Context *ctx, ChipConfig &cc, PipId pip)
+{
+ std::string tile = ctx->getPipTilename(pip);
+ std::string source = get_trellis_wirename(ctx, pip.location, ctx->getPipSrcWire(pip));
+ std::string sink = get_trellis_wirename(ctx, pip.location, ctx->getPipDstWire(pip));
+ cc.tiles[tile].add_arc(sink, source);
+}
+
void write_bitstream(Context *ctx, std::string base_config_file, std::string text_config_file)
{
ChipConfig cc;
@@ -165,10 +484,16 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
for (auto pip : ctx->getPips()) {
if (ctx->getBoundPipNet(pip) != nullptr) {
if (ctx->getPipClass(pip) == 0) { // ignore fixed pips
- std::string tile = ctx->getPipTilename(pip);
std::string source = get_trellis_wirename(ctx, pip.location, ctx->getPipSrcWire(pip));
- std::string sink = get_trellis_wirename(ctx, pip.location, ctx->getPipDstWire(pip));
- cc.tiles[tile].add_arc(sink, source);
+ if (source.find("CLKI_PLL") != std::string::npos) {
+ // Special case - must set pip in all relevant tiles
+ for (auto equiv_pip : ctx->getPipsUphill(ctx->getPipDstWire(pip))) {
+ if (ctx->getPipSrcWire(equiv_pip) == ctx->getPipSrcWire(pip))
+ set_pip(ctx, cc, equiv_pip);
+ }
+ } else {
+ set_pip(ctx, cc, pip);
+ }
}
}
}
@@ -244,19 +569,64 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
cc.tiles[tname].add_enum(slice + ".REG1.REGSET",
str_or_default(ci->params, ctx->id("REG1_REGSET"), "RESET"));
cc.tiles[tname].add_enum(slice + ".CEMUX", str_or_default(ci->params, ctx->id("CEMUX"), "1"));
- NetInfo *lsrnet = nullptr;
- if (ci->ports.find(ctx->id("LSR")) != ci->ports.end() && ci->ports.at(ctx->id("LSR")).net != nullptr)
- lsrnet = ci->ports.at(ctx->id("LSR")).net;
- if (ctx->getBoundWireNet(ctx->getWireByName(
- ctx->id(fmt_str("X" << bel.location.x << "/Y" << bel.location.y << "/LSR0")))) == lsrnet) {
- cc.tiles[tname].add_enum("LSR0.SRMODE", str_or_default(ci->params, ctx->id("SRMODE"), "LSR_OVER_CE"));
- cc.tiles[tname].add_enum("LSR0.LSRMUX", str_or_default(ci->params, ctx->id("LSRMUX"), "LSR"));
- } else if (ctx->getBoundWireNet(ctx->getWireByName(ctx->id(
- fmt_str("X" << bel.location.x << "/Y" << bel.location.y << "/LSR1")))) == lsrnet) {
- cc.tiles[tname].add_enum("LSR1.SRMODE", str_or_default(ci->params, ctx->id("SRMODE"), "LSR_OVER_CE"));
- cc.tiles[tname].add_enum("LSR1.LSRMUX", str_or_default(ci->params, ctx->id("LSRMUX"), "LSR"));
+
+ if (ci->sliceInfo.using_dff) {
+ NetInfo *lsrnet = nullptr;
+ if (ci->ports.find(ctx->id("LSR")) != ci->ports.end() && ci->ports.at(ctx->id("LSR")).net != nullptr)
+ lsrnet = ci->ports.at(ctx->id("LSR")).net;
+ if (ctx->getBoundWireNet(ctx->getWireByName(
+ ctx->id(fmt_str("X" << bel.location.x << "/Y" << bel.location.y << "/LSR0")))) == lsrnet) {
+ cc.tiles[tname].add_enum("LSR0.SRMODE",
+ str_or_default(ci->params, ctx->id("SRMODE"), "LSR_OVER_CE"));
+ cc.tiles[tname].add_enum("LSR0.LSRMUX", str_or_default(ci->params, ctx->id("LSRMUX"), "LSR"));
+ } else if (ctx->getBoundWireNet(ctx->getWireByName(ctx->id(
+ fmt_str("X" << bel.location.x << "/Y" << bel.location.y << "/LSR1")))) == lsrnet) {
+ cc.tiles[tname].add_enum("LSR1.SRMODE",
+ str_or_default(ci->params, ctx->id("SRMODE"), "LSR_OVER_CE"));
+ cc.tiles[tname].add_enum("LSR1.LSRMUX", str_or_default(ci->params, ctx->id("LSRMUX"), "LSR"));
+ }
+
+ NetInfo *clknet = nullptr;
+ if (ci->ports.find(ctx->id("CLK")) != ci->ports.end() && ci->ports.at(ctx->id("CLK")).net != nullptr)
+ clknet = ci->ports.at(ctx->id("CLK")).net;
+ if (ctx->getBoundWireNet(ctx->getWireByName(
+ ctx->id(fmt_str("X" << bel.location.x << "/Y" << bel.location.y << "/CLK0")))) == clknet) {
+ cc.tiles[tname].add_enum("CLK0.CLKMUX", str_or_default(ci->params, ctx->id("CLKMUX"), "CLK"));
+ } else if (ctx->getBoundWireNet(ctx->getWireByName(ctx->id(
+ fmt_str("X" << bel.location.x << "/Y" << bel.location.y << "/CLK1")))) == clknet) {
+ cc.tiles[tname].add_enum("CLK1.CLKMUX", str_or_default(ci->params, ctx->id("CLKMUX"), "CLK"));
+ }
+ }
+
+ if (str_or_default(ci->params, ctx->id("MODE"), "LOGIC") == "CCU2") {
+ cc.tiles[tname].add_enum(slice + ".CCU2.INJECT1_0",
+ str_or_default(ci->params, ctx->id("INJECT1_0"), "YES"));
+ cc.tiles[tname].add_enum(slice + ".CCU2.INJECT1_1",
+ str_or_default(ci->params, ctx->id("INJECT1_1"), "YES"));
+ } else {
+ // Don't interfere with cascade mux wiring
+ cc.tiles[tname].add_enum(slice + ".CCU2.INJECT1_0",
+ str_or_default(ci->params, ctx->id("INJECT1_0"), "_NONE_"));
+ cc.tiles[tname].add_enum(slice + ".CCU2.INJECT1_1",
+ str_or_default(ci->params, ctx->id("INJECT1_1"), "_NONE_"));
}
- // TODO: CLKMUX, CEMUX, carry
+
+ if (str_or_default(ci->params, ctx->id("MODE"), "LOGIC") == "DPRAM" && slice == "SLICEA") {
+ cc.tiles[tname].add_enum(slice + ".WREMUX", str_or_default(ci->params, ctx->id("WREMUX"), "WRE"));
+
+ std::string wckmux = str_or_default(ci->params, ctx->id("WCKMUX"), "WCK");
+ wckmux = (wckmux == "WCK") ? "CLK" : wckmux;
+ cc.tiles[tname].add_enum("CLK1.CLKMUX", wckmux);
+ }
+
+ // Tie unused inputs high
+ for (auto input : {id_A0, id_B0, id_C0, id_D0, id_A1, id_B1, id_C1, id_D1}) {
+ if (ci->ports.find(input) == ci->ports.end() || ci->ports.at(input).net == nullptr) {
+ cc.tiles[tname].add_enum(slice + "." + input.str(ctx) + "MUX", "1");
+ }
+ }
+
+ // TODO: CLKMUX
} else if (ci->type == ctx->id("TRELLIS_IO")) {
std::string pio = ctx->locInfo(bel)->bel_data[bel.index].name.get();
std::string iotype = str_or_default(ci->attrs, ctx->id("IO_TYPE"), "LVCMOS33");
@@ -294,11 +664,348 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
if (dir == "INPUT" && !is_differential(ioType_from_str(iotype))) {
cc.tiles[pio_tile].add_enum(pio + ".HYSTERESIS", "ON");
}
+ if (ci->attrs.count(ctx->id("SLEWRATE")))
+ cc.tiles[pio_tile].add_enum(pio + ".SLEWRATE", str_or_default(ci->attrs, ctx->id("SLEWRATE"), "SLOW"));
+ } else if (ci->type == ctx->id("DCCA")) {
+ // Nothing to do
+ } else if (ci->type == ctx->id("DP16KD")) {
+ TileGroup tg;
+ Loc loc = ctx->getBelLocation(ci->bel);
+ tg.tiles = get_bram_tiles(ctx, ci->bel);
+ std::string ebr = "EBR" + std::to_string(loc.z);
+
+ tg.config.add_enum(ebr + ".MODE", "DP16KD");
+
+ auto csd_a = str_to_bitvector(str_or_default(ci->params, ctx->id("CSDECODE_A"), "0b000"), 3),
+ csd_b = str_to_bitvector(str_or_default(ci->params, ctx->id("CSDECODE_B"), "0b000"), 3);
+
+ tg.config.add_enum(ebr + ".DP16KD.DATA_WIDTH_A", str_or_default(ci->params, ctx->id("DATA_WIDTH_A"), "18"));
+ tg.config.add_enum(ebr + ".DP16KD.DATA_WIDTH_B", str_or_default(ci->params, ctx->id("DATA_WIDTH_B"), "18"));
+
+ tg.config.add_enum(ebr + ".DP16KD.WRITEMODE_A",
+ str_or_default(ci->params, ctx->id("WRITEMODE_A"), "NORMAL"));
+ tg.config.add_enum(ebr + ".DP16KD.WRITEMODE_B",
+ str_or_default(ci->params, ctx->id("WRITEMODE_B"), "NORMAL"));
+
+ tg.config.add_enum(ebr + ".REGMODE_A", str_or_default(ci->params, ctx->id("REGMODE_A"), "NOREG"));
+ tg.config.add_enum(ebr + ".REGMODE_B", str_or_default(ci->params, ctx->id("REGMODE_B"), "NOREG"));
+
+ tg.config.add_enum(ebr + ".RESETMODE", str_or_default(ci->params, ctx->id("RESETMODE"), "SYNC"));
+ tg.config.add_enum(ebr + ".ASYNC_RESET_RELEASE",
+ str_or_default(ci->params, ctx->id("ASYNC_RESET_RELEASE"), "SYNC"));
+ tg.config.add_enum(ebr + ".GSR", str_or_default(ci->params, ctx->id("GSR"), "DISABLED"));
+
+ tg.config.add_word(ebr + ".WID",
+ int_to_bitvector(bit_reverse(int_or_default(ci->attrs, ctx->id("WID"), 0), 9), 9));
+
+ // Tie signals as appropriate
+ for (auto port : ci->ports) {
+ if (port.second.net == nullptr && port.second.type == PORT_IN) {
+ if (port.first == id_CLKA || port.first == id_CLKB || port.first == id_WEA ||
+ port.first == id_WEB || port.first == id_RSTA || port.first == id_RSTB) {
+ // CIB clock or LSR. Tie to "1" (also 0 in prjtrellis db?) in CIB
+ // If MUX doesn't exist, set to INV to emulate default 0
+ tie_cib_signal(ctx, cc, ctx->getBelPinWire(ci->bel, port.first), true);
+ if (!ci->params.count(ctx->id(port.first.str(ctx) + "MUX")))
+ ci->params[ctx->id(port.first.str(ctx) + "MUX")] = "INV";
+ } else if (port.first == id_CEA || port.first == id_CEB || port.first == id_OCEA ||
+ port.first == id_OCEB) {
+ // CIB CE. Tie to "1" in CIB
+ // If MUX doesn't exist, set to passthru to emulate default 1
+ tie_cib_signal(ctx, cc, ctx->getBelPinWire(ci->bel, port.first), true);
+ if (!ci->params.count(ctx->id(port.first.str(ctx) + "MUX")))
+ ci->params[ctx->id(port.first.str(ctx) + "MUX")] = port.first.str(ctx);
+ } else if (port.first == id_CSA0 || port.first == id_CSA1 || port.first == id_CSA2 ||
+ port.first == id_CSB0 || port.first == id_CSB1 || port.first == id_CSB2) {
+ // CIB CE. Tie to "1" in CIB.
+ // If MUX doesn't exist, set to INV to emulate default 0
+ tie_cib_signal(ctx, cc, ctx->getBelPinWire(ci->bel, port.first), true);
+ if (!ci->params.count(ctx->id(port.first.str(ctx) + "MUX")))
+ ci->params[ctx->id(port.first.str(ctx) + "MUX")] = "INV";
+ } else {
+ // CIB ABCD signal
+ // Tie signals low unless explicit MUX param specified
+ bool value = bool_or_default(ci->params, ctx->id(port.first.str(ctx) + "MUX"), false);
+ tie_cib_signal(ctx, cc, ctx->getBelPinWire(ci->bel, port.first), value);
+ }
+ }
+ }
+
+ // Invert CSDECODE bits to emulate inversion muxes on CSA/CSB signals
+ for (auto port : {std::make_pair("CSA", std::ref(csd_a)), std::make_pair("CSB", std::ref(csd_b))}) {
+ for (int bit = 0; bit < 3; bit++) {
+ std::string sig = port.first + std::to_string(bit);
+ if (str_or_default(ci->params, ctx->id(sig + "MUX"), sig) == "INV")
+ port.second.at(bit) = !port.second.at(bit);
+ }
+ }
+
+ tg.config.add_enum(ebr + ".CLKAMUX", str_or_default(ci->params, ctx->id("CLKAMUX"), "CLKA"));
+ tg.config.add_enum(ebr + ".CLKBMUX", str_or_default(ci->params, ctx->id("CLKBMUX"), "CLKB"));
+
+ tg.config.add_enum(ebr + ".RSTAMUX", str_or_default(ci->params, ctx->id("RSTAMUX"), "RSTA"));
+ tg.config.add_enum(ebr + ".RSTBMUX", str_or_default(ci->params, ctx->id("RSTBMUX"), "RSTB"));
+ tg.config.add_enum(ebr + ".WEAMUX", str_or_default(ci->params, ctx->id("WEAMUX"), "WEA"));
+ tg.config.add_enum(ebr + ".WEBMUX", str_or_default(ci->params, ctx->id("WEBMUX"), "WEB"));
+
+ tg.config.add_enum(ebr + ".CEAMUX", str_or_default(ci->params, ctx->id("CEAMUX"), "CEA"));
+ tg.config.add_enum(ebr + ".CEBMUX", str_or_default(ci->params, ctx->id("CEBMUX"), "CEB"));
+ tg.config.add_enum(ebr + ".OCEAMUX", str_or_default(ci->params, ctx->id("OCEAMUX"), "OCEA"));
+ tg.config.add_enum(ebr + ".OCEBMUX", str_or_default(ci->params, ctx->id("OCEBMUX"), "OCEB"));
+
+ tg.config.add_word(ebr + ".CSDECODE_A", csd_a);
+ tg.config.add_word(ebr + ".CSDECODE_B", csd_b);
+
+ std::vector<uint16_t> init_data;
+ init_data.resize(2048, 0x0);
+ // INIT_00 .. INIT_3F
+ for (int i = 0; i <= 0x3F; i++) {
+ IdString param = ctx->id("INITVAL_" +
+ fmt_str(std::hex << std::uppercase << std::setw(2) << std::setfill('0') << i));
+ auto value = parse_init_str(str_or_default(ci->params, param, "0"), 320);
+ for (int j = 0; j < 16; j++) {
+ // INIT parameter consists of 16 18-bit words with 2-bit padding
+ int ofs = 20 * j;
+ for (int k = 0; k < 18; k++) {
+ if (value.at(ofs + k))
+ init_data.at(i * 32 + j * 2 + (k / 9)) |= (1 << (k % 9));
+ }
+ }
+ }
+ int wid = int_or_default(ci->attrs, ctx->id("WID"), 0);
+ NPNR_ASSERT(!cc.bram_data.count(wid));
+ cc.bram_data[wid] = init_data;
+ cc.tilegroups.push_back(tg);
+ } else if (ci->type == id_MULT18X18D) {
+ TileGroup tg;
+ Loc loc = ctx->getBelLocation(ci->bel);
+ tg.tiles = get_dsp_tiles(ctx, ci->bel);
+ std::string dsp = "MULT18_" + std::to_string(loc.z);
+ tg.config.add_enum(dsp + ".REG_INPUTA_CLK", str_or_default(ci->params, ctx->id("REG_INPUTA_CLK"), "NONE"));
+ tg.config.add_enum(dsp + ".REG_INPUTA_CE", str_or_default(ci->params, ctx->id("REG_INPUTA_CE"), "CE0"));
+ tg.config.add_enum(dsp + ".REG_INPUTA_RST", str_or_default(ci->params, ctx->id("REG_INPUTA_RST"), "RST0"));
+ tg.config.add_enum(dsp + ".REG_INPUTB_CLK", str_or_default(ci->params, ctx->id("REG_INPUTB_CLK"), "NONE"));
+ tg.config.add_enum(dsp + ".REG_INPUTB_CE", str_or_default(ci->params, ctx->id("REG_INPUTB_CE"), "CE0"));
+ tg.config.add_enum(dsp + ".REG_INPUTB_RST", str_or_default(ci->params, ctx->id("REG_INPUTB_RST"), "RST0"));
+ tg.config.add_enum(dsp + ".REG_INPUTC_CLK", str_or_default(ci->params, ctx->id("REG_INPUTC_CLK"), "NONE"));
+ tg.config.add_enum(dsp + ".REG_PIPELINE_CLK",
+ str_or_default(ci->params, ctx->id("REG_PIPELINE_CLK"), "NONE"));
+ tg.config.add_enum(dsp + ".REG_PIPELINE_CE", str_or_default(ci->params, ctx->id("REG_PIPELINE_CE"), "CE0"));
+ tg.config.add_enum(dsp + ".REG_PIPELINE_RST",
+ str_or_default(ci->params, ctx->id("REG_PIPELINE_RST"), "RST0"));
+ tg.config.add_enum(dsp + ".REG_OUTPUT_CLK", str_or_default(ci->params, ctx->id("REG_OUTPUT_CLK"), "NONE"));
+ if (dsp == "MULT18_0" || dsp == "MULT18_4")
+ tg.config.add_enum(dsp + ".REG_OUTPUT_RST",
+ str_or_default(ci->params, ctx->id("REG_OUTPUT_RST"), "RST0"));
+
+ tg.config.add_enum(dsp + ".CLK0_DIV", str_or_default(ci->params, ctx->id("CLK0_DIV"), "ENABLED"));
+ tg.config.add_enum(dsp + ".CLK1_DIV", str_or_default(ci->params, ctx->id("CLK1_DIV"), "ENABLED"));
+ tg.config.add_enum(dsp + ".CLK2_DIV", str_or_default(ci->params, ctx->id("CLK2_DIV"), "ENABLED"));
+ tg.config.add_enum(dsp + ".CLK3_DIV", str_or_default(ci->params, ctx->id("CLK3_DIV"), "ENABLED"));
+ tg.config.add_enum(dsp + ".GSR", str_or_default(ci->params, ctx->id("GSR"), "ENABLED"));
+ tg.config.add_enum(dsp + ".SOURCEB_MODE", str_or_default(ci->params, ctx->id("SOURCEB_MODE"), "B_SHIFT"));
+ tg.config.add_enum(dsp + ".RESETMODE", str_or_default(ci->params, ctx->id("RESETMODE"), "SYNC"));
+
+ tg.config.add_enum(dsp + ".MODE", "MULT18X18D");
+ if (str_or_default(ci->params, ctx->id("REG_OUTPUT_CLK"), "NONE") == "NONE")
+ tg.config.add_enum(dsp + ".CIBOUT_BYP", "ON");
+
+ if (loc.z < 4)
+ tg.config.add_enum("DSP_LEFT.CIBOUT", "ON");
+ else
+ tg.config.add_enum("DSP_RIGHT.CIBOUT", "ON");
+
+ // Some muxes default to INV, make all pass-thru
+ for (auto port : {"CLK", "CE", "RST"}) {
+ for (int i = 0; i < 4; i++) {
+ std::string sig = port + std::to_string(i);
+ tg.config.add_enum(dsp + "." + sig + "MUX", sig);
+ }
+ }
+
+ tieoff_dsp_ports(ctx, cc, ci);
+ cc.tilegroups.push_back(tg);
+
+ } else if (ci->type == id_ALU54B) {
+ TileGroup tg;
+ Loc loc = ctx->getBelLocation(ci->bel);
+ tg.tiles = get_dsp_tiles(ctx, ci->bel);
+ std::string dsp = "ALU54_" + std::to_string(loc.z);
+ tg.config.add_enum(dsp + ".REG_INPUTC0_CLK",
+ str_or_default(ci->params, ctx->id("REG_INPUTC0_CLK"), "NONE"));
+ tg.config.add_enum(dsp + ".REG_INPUTC1_CLK",
+ str_or_default(ci->params, ctx->id("REG_INPUTC1_CLK"), "NONE"));
+ tg.config.add_enum(dsp + ".REG_OPCODEOP0_0_CLK",
+ str_or_default(ci->params, ctx->id("REG_OPCODEOP0_0_CLK"), "NONE"));
+ tg.config.add_enum(dsp + ".REG_OPCODEOP0_0_CE",
+ str_or_default(ci->params, ctx->id("REG_OPCODEOP0_0_CE"), "CE0"));
+ tg.config.add_enum(dsp + ".REG_OPCODEOP0_0_RST",
+ str_or_default(ci->params, ctx->id("REG_OPCODEOP0_0_RST"), "RST0"));
+ tg.config.add_enum(dsp + ".REG_OPCODEOP1_0_CLK",
+ str_or_default(ci->params, ctx->id("REG_OPCODEOP1_0_CLK"), "NONE"));
+ tg.config.add_enum(dsp + ".REG_OPCODEOP0_1_CLK",
+ str_or_default(ci->params, ctx->id("REG_OPCODEOP0_1_CLK"), "NONE"));
+ tg.config.add_enum(dsp + ".REG_OPCODEOP0_1_CE",
+ str_or_default(ci->params, ctx->id("REG_OPCODEOP0_1_CE"), "CE0"));
+ tg.config.add_enum(dsp + ".REG_OPCODEOP0_1_RST",
+ str_or_default(ci->params, ctx->id("REG_OPCODEOP0_1_RST"), "RST0"));
+ tg.config.add_enum(dsp + ".REG_OPCODEIN_0_CLK",
+ str_or_default(ci->params, ctx->id("REG_OPCODEIN_0_CLK"), "NONE"));
+ tg.config.add_enum(dsp + ".REG_OPCODEIN_0_CE",
+ str_or_default(ci->params, ctx->id("REG_OPCODEIN_0_CE"), "CE0"));
+ tg.config.add_enum(dsp + ".REG_OPCODEIN_0_RST",
+ str_or_default(ci->params, ctx->id("REG_OPCODEIN_0_RST"), "RST0"));
+ tg.config.add_enum(dsp + ".REG_OPCODEIN_1_CLK",
+ str_or_default(ci->params, ctx->id("REG_OPCODEIN_1_CLK"), "NONE"));
+ tg.config.add_enum(dsp + ".REG_OPCODEIN_1_CE",
+ str_or_default(ci->params, ctx->id("REG_OPCODEIN_1_CE"), "CE0"));
+ tg.config.add_enum(dsp + ".REG_OPCODEIN_1_RST",
+ str_or_default(ci->params, ctx->id("REG_OPCODEIN_1_RST"), "RST0"));
+ tg.config.add_enum(dsp + ".REG_OUTPUT0_CLK",
+ str_or_default(ci->params, ctx->id("REG_OUTPUT0_CLK"), "NONE"));
+ tg.config.add_enum(dsp + ".REG_OUTPUT1_CLK",
+ str_or_default(ci->params, ctx->id("REG_OUTPUT1_CLK"), "NONE"));
+ tg.config.add_enum(dsp + ".REG_FLAG_CLK", str_or_default(ci->params, ctx->id("REG_FLAG_CLK"), "NONE"));
+ tg.config.add_enum(dsp + ".MCPAT_SOURCE", str_or_default(ci->params, ctx->id("MCPAT_SOURCE"), "STATIC"));
+ tg.config.add_enum(dsp + ".MASKPAT_SOURCE",
+ str_or_default(ci->params, ctx->id("MASKPAT_SOURCE"), "STATIC"));
+ tg.config.add_word(dsp + ".MASK01",
+ parse_init_str(str_or_default(ci->params, ctx->id("MASK01"), "0x00000000000000"), 56));
+ tg.config.add_enum(dsp + ".CLK0_DIV", str_or_default(ci->params, ctx->id("CLK0_DIV"), "ENABLED"));
+ tg.config.add_enum(dsp + ".CLK1_DIV", str_or_default(ci->params, ctx->id("CLK1_DIV"), "ENABLED"));
+ tg.config.add_enum(dsp + ".CLK2_DIV", str_or_default(ci->params, ctx->id("CLK2_DIV"), "ENABLED"));
+ tg.config.add_enum(dsp + ".CLK3_DIV", str_or_default(ci->params, ctx->id("CLK3_DIV"), "ENABLED"));
+ tg.config.add_word(dsp + ".MCPAT",
+ parse_init_str(str_or_default(ci->params, ctx->id("MCPAT"), "0x00000000000000"), 56));
+ tg.config.add_word(dsp + ".MASKPAT",
+ parse_init_str(str_or_default(ci->params, ctx->id("MASKPAT"), "0x00000000000000"), 56));
+ tg.config.add_word(dsp + ".RNDPAT",
+ parse_init_str(str_or_default(ci->params, ctx->id("RNDPAT"), "0x00000000000000"), 56));
+ tg.config.add_enum(dsp + ".GSR", str_or_default(ci->params, ctx->id("GSR"), "ENABLED"));
+ tg.config.add_enum(dsp + ".RESETMODE", str_or_default(ci->params, ctx->id("RESETMODE"), "SYNC"));
+ tg.config.add_enum(dsp + ".FORCE_ZERO_BARREL_SHIFT",
+ str_or_default(ci->params, ctx->id("FORCE_ZERO_BARREL_SHIFT"), "DISABLED"));
+ tg.config.add_enum(dsp + ".LEGACY", str_or_default(ci->params, ctx->id("LEGACY"), "DISABLED"));
+
+ tg.config.add_enum(dsp + ".MODE", "ALU54B");
+
+ if (loc.z < 4)
+ tg.config.add_enum("DSP_LEFT.CIBOUT", "ON");
+ else
+ tg.config.add_enum("DSP_RIGHT.CIBOUT", "ON");
+ if (str_or_default(ci->params, ctx->id("REG_FLAG_CLK"), "NONE") == "NONE") {
+ if (dsp == "ALU54_7") {
+ tg.config.add_enum("MULT18_5.CIBOUT_BYP", "ON");
+ } else if (dsp == "ALU54_3") {
+ tg.config.add_enum("MULT18_5.CIBOUT_BYP", "ON");
+ }
+ }
+ if (str_or_default(ci->params, ctx->id("REG_OUTPUT0_CLK"), "NONE") == "NONE") {
+ if (dsp == "ALU54_7") {
+ tg.config.add_enum("MULT18_4.CIBOUT_BYP", "ON");
+ } else if (dsp == "ALU54_3") {
+ tg.config.add_enum("MULT18_0.CIBOUT_BYP", "ON");
+ }
+ }
+ tieoff_dsp_ports(ctx, cc, ci);
+ cc.tilegroups.push_back(tg);
+ } else if (ci->type == id_EHXPLLL) {
+ TileGroup tg;
+ tg.tiles = get_pll_tiles(ctx, ci->bel);
+
+ tg.config.add_enum("MODE", "EHXPLLL");
+
+ tg.config.add_word("CLKI_DIV", int_to_bitvector(int_or_default(ci->params, ctx->id("CLKI_DIV"), 1) - 1, 7));
+ tg.config.add_word("CLKFB_DIV",
+ int_to_bitvector(int_or_default(ci->params, ctx->id("CLKFB_DIV"), 1) - 1, 7));
+
+ tg.config.add_enum("CLKOP_ENABLE", str_or_default(ci->params, ctx->id("CLKOP_ENABLE"), "ENABLED"));
+ tg.config.add_enum("CLKOS_ENABLE", str_or_default(ci->params, ctx->id("CLKOS_ENABLE"), "ENABLED"));
+ tg.config.add_enum("CLKOS2_ENABLE", str_or_default(ci->params, ctx->id("CLKOS2_ENABLE"), "ENABLED"));
+ tg.config.add_enum("CLKOS3_ENABLE", str_or_default(ci->params, ctx->id("CLKOS3_ENABLE"), "ENABLED"));
+
+ for (std::string out : {"CLKOP", "CLKOS", "CLKOS2", "CLKOS3"}) {
+ tg.config.add_word(out + "_DIV",
+ int_to_bitvector(int_or_default(ci->params, ctx->id(out + "_DIV"), 8) - 1, 7));
+ tg.config.add_word(out + "_CPHASE",
+ int_to_bitvector(int_or_default(ci->params, ctx->id(out + "_CPHASE"), 0), 7));
+ tg.config.add_word(out + "_FPHASE",
+ int_to_bitvector(int_or_default(ci->params, ctx->id(out + "_FPHASE"), 0), 3));
+ }
+
+ tg.config.add_enum("FEEDBK_PATH", str_or_default(ci->params, ctx->id("FEEDBK_PATH"), "CLKOP"));
+ tg.config.add_enum("CLKOP_TRIM_POL", str_or_default(ci->params, ctx->id("CLKOP_TRIM_POL"), "RISING"));
+ tg.config.add_enum("CLKOP_TRIM_DELAY", str_or_default(ci->params, ctx->id("CLKOP_TRIM_DELAY"), "0"));
+ tg.config.add_enum("CLKOS_TRIM_POL", str_or_default(ci->params, ctx->id("CLKOS_TRIM_POL"), "RISING"));
+ tg.config.add_enum("CLKOS_TRIM_DELAY", str_or_default(ci->params, ctx->id("CLKOS_TRIM_DELAY"), "0"));
+
+ tg.config.add_enum("OUTDIVIDER_MUXA", str_or_default(ci->params, ctx->id("OUTDIVIDER_MUXA"),
+ get_net_or_empty(ci, id_CLKOP) ? "DIVA" : "REFCLK"));
+ tg.config.add_enum("OUTDIVIDER_MUXB", str_or_default(ci->params, ctx->id("OUTDIVIDER_MUXB"),
+ get_net_or_empty(ci, id_CLKOP) ? "DIVB" : "REFCLK"));
+ tg.config.add_enum("OUTDIVIDER_MUXC", str_or_default(ci->params, ctx->id("OUTDIVIDER_MUXC"),
+ get_net_or_empty(ci, id_CLKOP) ? "DIVC" : "REFCLK"));
+ tg.config.add_enum("OUTDIVIDER_MUXD", str_or_default(ci->params, ctx->id("OUTDIVIDER_MUXD"),
+ get_net_or_empty(ci, id_CLKOP) ? "DIVD" : "REFCLK"));
+
+ tg.config.add_word("PLL_LOCK_MODE",
+ int_to_bitvector(int_or_default(ci->params, ctx->id("PLL_LOCK_MODE"), 0), 3));
+
+ tg.config.add_enum("STDBY_ENABLE", str_or_default(ci->params, ctx->id("STDBY_ENABLE"), "DISABLED"));
+ tg.config.add_enum("REFIN_RESET", str_or_default(ci->params, ctx->id("REFIN_RESET"), "DISABLED"));
+ tg.config.add_enum("SYNC_ENABLE", str_or_default(ci->params, ctx->id("SYNC_ENABLE"), "DISABLED"));
+ tg.config.add_enum("INT_LOCK_STICKY", str_or_default(ci->params, ctx->id("INT_LOCK_STICKY"), "ENABLED"));
+ tg.config.add_enum("DPHASE_SOURCE", str_or_default(ci->params, ctx->id("DPHASE_SOURCE"), "DISABLED"));
+ tg.config.add_enum("PLLRST_ENA", str_or_default(ci->params, ctx->id("PLLRST_ENA"), "DISABLED"));
+ tg.config.add_enum("INTFB_WAKE", str_or_default(ci->params, ctx->id("INTFB_WAKE"), "DISABLED"));
+
+ tg.config.add_word("KVCO", int_to_bitvector(int_or_default(ci->attrs, ctx->id("KVCO"), 0), 3));
+ tg.config.add_word("LPF_CAPACITOR",
+ int_to_bitvector(int_or_default(ci->attrs, ctx->id("LPF_CAPACITOR"), 0), 2));
+ tg.config.add_word("LPF_RESISTOR",
+ int_to_bitvector(int_or_default(ci->attrs, ctx->id("LPF_RESISTOR"), 0), 7));
+ tg.config.add_word("ICP_CURRENT",
+ int_to_bitvector(int_or_default(ci->attrs, ctx->id("ICP_CURRENT"), 0), 5));
+ tg.config.add_word("FREQ_LOCK_ACCURACY",
+ int_to_bitvector(int_or_default(ci->attrs, ctx->id("FREQ_LOCK_ACCURACY"), 0), 2));
+
+ tg.config.add_word("MFG_GMC_GAIN",
+ int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_GMC_GAIN"), 0), 3));
+ tg.config.add_word("MFG_GMC_TEST",
+ int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_GMC_TEST"), 14), 4));
+ tg.config.add_word("MFG1_TEST", int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG1_TEST"), 0), 3));
+ tg.config.add_word("MFG2_TEST", int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG2_TEST"), 0), 3));
+
+ tg.config.add_word("MFG_FORCE_VFILTER",
+ int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_FORCE_VFILTER"), 0), 1));
+ tg.config.add_word("MFG_ICP_TEST",
+ int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_ICP_TEST"), 0), 1));
+ tg.config.add_word("MFG_EN_UP", int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_EN_UP"), 0), 1));
+ tg.config.add_word("MFG_FLOAT_ICP",
+ int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_FLOAT_ICP"), 0), 1));
+ tg.config.add_word("MFG_GMC_PRESET",
+ int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_GMC_PRESET"), 0), 1));
+ tg.config.add_word("MFG_LF_PRESET",
+ int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_LF_PRESET"), 0), 1));
+ tg.config.add_word("MFG_GMC_RESET",
+ int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_GMC_RESET"), 0), 1));
+ tg.config.add_word("MFG_LF_RESET",
+ int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_LF_RESET"), 0), 1));
+ tg.config.add_word("MFG_LF_RESGRND",
+ int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_LF_RESGRND"), 0), 1));
+ tg.config.add_word("MFG_GMCREF_SEL",
+ int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_GMCREF_SEL"), 0), 2));
+ tg.config.add_word("MFG_ENABLE_FILTEROPAMP",
+ int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_ENABLE_FILTEROPAMP"), 0), 1));
+
+ cc.tilegroups.push_back(tg);
} else {
NPNR_ASSERT_FALSE("unsupported cell type");
}
}
+ // Fixup tile names
+ fix_tile_names(ctx, cc);
// Configure chip
if (!text_config_file.empty()) {
std::ofstream out_config(text_config_file);
diff --git a/ecp5/cells.cc b/ecp5/cells.cc
index e3532f36..31839ee4 100644
--- a/ecp5/cells.cc
+++ b/ecp5/cells.cc
@@ -124,6 +124,32 @@ std::unique_ptr<CellInfo> create_ecp5_cell(Context *ctx, IdString type, std::str
add_port(ctx, new_cell.get(), "C", PORT_IN);
add_port(ctx, new_cell.get(), "D", PORT_IN);
add_port(ctx, new_cell.get(), "Z", PORT_OUT);
+ } else if (type == ctx->id("CCU2C")) {
+ new_cell->params[ctx->id("INIT0")] = "0";
+ new_cell->params[ctx->id("INIT1")] = "0";
+ new_cell->params[ctx->id("INJECT1_0")] = "YES";
+ new_cell->params[ctx->id("INJECT1_1")] = "YES";
+
+ add_port(ctx, new_cell.get(), "CIN", PORT_IN);
+
+ add_port(ctx, new_cell.get(), "A0", PORT_IN);
+ add_port(ctx, new_cell.get(), "B0", PORT_IN);
+ add_port(ctx, new_cell.get(), "C0", PORT_IN);
+ add_port(ctx, new_cell.get(), "D0", PORT_IN);
+
+ add_port(ctx, new_cell.get(), "A1", PORT_IN);
+ add_port(ctx, new_cell.get(), "B1", PORT_IN);
+ add_port(ctx, new_cell.get(), "C1", PORT_IN);
+ add_port(ctx, new_cell.get(), "D1", PORT_IN);
+
+ add_port(ctx, new_cell.get(), "S0", PORT_OUT);
+ add_port(ctx, new_cell.get(), "S1", PORT_OUT);
+ add_port(ctx, new_cell.get(), "COUT", PORT_OUT);
+
+ } else if (type == ctx->id("DCCA")) {
+ add_port(ctx, new_cell.get(), "CLKI", PORT_IN);
+ add_port(ctx, new_cell.get(), "CLKO", PORT_OUT);
+ add_port(ctx, new_cell.get(), "CE", PORT_IN);
} else {
log_error("unable to create ECP5 cell of type %s", type.c_str(ctx));
}
@@ -159,6 +185,8 @@ void ff_to_slice(Context *ctx, CellInfo *ff, CellInfo *lc, int index, bool drive
set_param_safe(has_ff, lc, ctx->id("GSR"), str_or_default(ff->params, ctx->id("GSR"), "DISABLED"));
set_param_safe(has_ff, lc, ctx->id("CEMUX"), str_or_default(ff->params, ctx->id("CEMUX"), "1"));
set_param_safe(has_ff, lc, ctx->id("LSRMUX"), str_or_default(ff->params, ctx->id("LSRMUX"), "LSR"));
+ set_param_safe(has_ff, lc, ctx->id("CLKMUX"), str_or_default(ff->params, ctx->id("CLKMUX"), "CLK"));
+
lc->params[ctx->id(reg + "_SD")] = driven_by_lut ? "1" : "0";
lc->params[ctx->id(reg + "_REGSET")] = str_or_default(ff->params, ctx->id("REGSET"), "RESET");
replace_port_safe(has_ff, ff, ctx->id("CLK"), lc, ctx->id("CLK"));
@@ -185,4 +213,176 @@ void lut_to_slice(Context *ctx, CellInfo *lut, CellInfo *lc, int index)
replace_port(lut, ctx->id("Z"), lc, ctx->id("F" + std::to_string(index)));
}
+void ccu2c_to_slice(Context *ctx, CellInfo *ccu, CellInfo *lc)
+{
+ lc->params[ctx->id("MODE")] = "CCU2";
+ lc->params[ctx->id("LUT0_INITVAL")] = str_or_default(ccu->params, ctx->id("INIT0"), "0");
+ lc->params[ctx->id("LUT1_INITVAL")] = str_or_default(ccu->params, ctx->id("INIT1"), "0");
+
+ lc->params[ctx->id("INJECT1_0")] = str_or_default(ccu->params, ctx->id("INJECT1_0"), "YES");
+ lc->params[ctx->id("INJECT1_1")] = str_or_default(ccu->params, ctx->id("INJECT1_1"), "YES");
+
+ replace_port(ccu, ctx->id("CIN"), lc, ctx->id("FCI"));
+
+ replace_port(ccu, ctx->id("A0"), lc, ctx->id("A0"));
+ replace_port(ccu, ctx->id("B0"), lc, ctx->id("B0"));
+ replace_port(ccu, ctx->id("C0"), lc, ctx->id("C0"));
+ replace_port(ccu, ctx->id("D0"), lc, ctx->id("D0"));
+
+ replace_port(ccu, ctx->id("A1"), lc, ctx->id("A1"));
+ replace_port(ccu, ctx->id("B1"), lc, ctx->id("B1"));
+ replace_port(ccu, ctx->id("C1"), lc, ctx->id("C1"));
+ replace_port(ccu, ctx->id("D1"), lc, ctx->id("D1"));
+
+ replace_port(ccu, ctx->id("S0"), lc, ctx->id("F0"));
+ replace_port(ccu, ctx->id("S1"), lc, ctx->id("F1"));
+
+ replace_port(ccu, ctx->id("COUT"), lc, ctx->id("FCO"));
+}
+
+void dram_to_ramw(Context *ctx, CellInfo *ram, CellInfo *lc)
+{
+ lc->params[ctx->id("MODE")] = "RAMW";
+ replace_port(ram, ctx->id("WAD[0]"), lc, ctx->id("D0"));
+ replace_port(ram, ctx->id("WAD[1]"), lc, ctx->id("B0"));
+ replace_port(ram, ctx->id("WAD[2]"), lc, ctx->id("C0"));
+ replace_port(ram, ctx->id("WAD[3]"), lc, ctx->id("A0"));
+
+ replace_port(ram, ctx->id("DI[0]"), lc, ctx->id("C1"));
+ replace_port(ram, ctx->id("DI[1]"), lc, ctx->id("A1"));
+ replace_port(ram, ctx->id("DI[2]"), lc, ctx->id("D1"));
+ replace_port(ram, ctx->id("DI[3]"), lc, ctx->id("B1"));
+}
+
+static unsigned get_dram_init(const Context *ctx, const CellInfo *ram, int bit)
+{
+ const std::string &idata = str_or_default(ram->params, ctx->id("INITVAL"),
+ "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx");
+ NPNR_ASSERT(idata.length() == 64);
+ unsigned value = 0;
+ for (int i = 0; i < 16; i++) {
+ char c = idata.at(63 - (4 * i + bit));
+ if (c == '1')
+ value |= (1 << i);
+ else
+ NPNR_ASSERT(c == '0' || c == 'x');
+ }
+ return value;
+}
+
+void dram_to_ram_slice(Context *ctx, CellInfo *ram, CellInfo *lc, CellInfo *ramw, int index)
+{
+ lc->params[ctx->id("MODE")] = "DPRAM";
+ lc->params[ctx->id("WREMUX")] = str_or_default(ram->params, ctx->id("WREMUX"), "WRE");
+ lc->params[ctx->id("WCKMUX")] = str_or_default(ram->params, ctx->id("WCKMUX"), "WCK");
+
+ unsigned permuted_init0 = 0, permuted_init1 = 0;
+ unsigned init0 = get_dram_init(ctx, ram, index * 2), init1 = get_dram_init(ctx, ram, index * 2 + 1);
+
+ for (int i = 0; i < 16; i++) {
+ int permuted_addr = 0;
+ if (i & 1)
+ permuted_addr |= 8;
+ if (i & 2)
+ permuted_addr |= 2;
+ if (i & 4)
+ permuted_addr |= 4;
+ if (i & 8)
+ permuted_addr |= 1;
+ if (init0 & (1 << permuted_addr))
+ permuted_init0 |= (1 << i);
+ if (init1 & (1 << permuted_addr))
+ permuted_init1 |= (1 << i);
+ }
+
+ lc->params[ctx->id("LUT0_INITVAL")] = std::to_string(permuted_init0);
+ lc->params[ctx->id("LUT1_INITVAL")] = std::to_string(permuted_init1);
+
+ if (ram->ports.count(ctx->id("RAD[0]"))) {
+ connect_port(ctx, ram->ports.at(ctx->id("RAD[0]")).net, lc, ctx->id("D0"));
+ connect_port(ctx, ram->ports.at(ctx->id("RAD[0]")).net, lc, ctx->id("D1"));
+ }
+ if (ram->ports.count(ctx->id("RAD[1]"))) {
+ connect_port(ctx, ram->ports.at(ctx->id("RAD[1]")).net, lc, ctx->id("B0"));
+ connect_port(ctx, ram->ports.at(ctx->id("RAD[1]")).net, lc, ctx->id("B1"));
+ }
+ if (ram->ports.count(ctx->id("RAD[2]"))) {
+ connect_port(ctx, ram->ports.at(ctx->id("RAD[2]")).net, lc, ctx->id("C0"));
+ connect_port(ctx, ram->ports.at(ctx->id("RAD[2]")).net, lc, ctx->id("C1"));
+ }
+ if (ram->ports.count(ctx->id("RAD[3]"))) {
+ connect_port(ctx, ram->ports.at(ctx->id("RAD[3]")).net, lc, ctx->id("A0"));
+ connect_port(ctx, ram->ports.at(ctx->id("RAD[3]")).net, lc, ctx->id("A1"));
+ }
+
+ if (ram->ports.count(ctx->id("WRE")))
+ connect_port(ctx, ram->ports.at(ctx->id("WRE")).net, lc, ctx->id("WRE"));
+ if (ram->ports.count(ctx->id("WCK")))
+ connect_port(ctx, ram->ports.at(ctx->id("WCK")).net, lc, ctx->id("WCK"));
+
+ connect_ports(ctx, ramw, id_WADO0, lc, id_WAD0);
+ connect_ports(ctx, ramw, id_WADO1, lc, id_WAD1);
+ connect_ports(ctx, ramw, id_WADO2, lc, id_WAD2);
+ connect_ports(ctx, ramw, id_WADO3, lc, id_WAD3);
+
+ if (index == 0) {
+ connect_ports(ctx, ramw, id_WDO0, lc, id_WD0);
+ connect_ports(ctx, ramw, id_WDO1, lc, id_WD1);
+
+ replace_port(ram, ctx->id("DO[0]"), lc, id_F0);
+ replace_port(ram, ctx->id("DO[1]"), lc, id_F1);
+
+ } else if (index == 1) {
+ connect_ports(ctx, ramw, id_WDO2, lc, id_WD0);
+ connect_ports(ctx, ramw, id_WDO3, lc, id_WD1);
+
+ replace_port(ram, ctx->id("DO[2]"), lc, id_F0);
+ replace_port(ram, ctx->id("DO[3]"), lc, id_F1);
+ } else {
+ NPNR_ASSERT_FALSE("bad DPRAM index");
+ }
+}
+
+void nxio_to_tr(Context *ctx, CellInfo *nxio, CellInfo *trio, std::vector<std::unique_ptr<CellInfo>> &created_cells,
+ std::unordered_set<IdString> &todelete_cells)
+{
+ if (nxio->type == ctx->id("$nextpnr_ibuf")) {
+ trio->params[ctx->id("DIR")] = "INPUT";
+ replace_port(nxio, ctx->id("O"), trio, ctx->id("O"));
+ } else if (nxio->type == ctx->id("$nextpnr_obuf")) {
+ trio->params[ctx->id("DIR")] = "OUTPUT";
+ replace_port(nxio, ctx->id("I"), trio, ctx->id("I"));
+ } else if (nxio->type == ctx->id("$nextpnr_iobuf")) {
+ // N.B. tristate will be dealt with below
+ trio->params[ctx->id("DIR")] = "BIDIR";
+ replace_port(nxio, ctx->id("I"), trio, ctx->id("I"));
+ replace_port(nxio, ctx->id("O"), trio, ctx->id("O"));
+ } else {
+ NPNR_ASSERT(false);
+ }
+ NetInfo *donet = trio->ports.at(ctx->id("I")).net;
+ CellInfo *tbuf = net_driven_by(
+ ctx, donet, [](const Context *ctx, const CellInfo *cell) { return cell->type == ctx->id("$_TBUF_"); },
+ ctx->id("Y"));
+ if (tbuf) {
+ replace_port(tbuf, ctx->id("I"), trio, ctx->id("I"));
+ // Need to invert E to form T
+ std::unique_ptr<CellInfo> inv_lut = create_ecp5_cell(ctx, ctx->id("LUT4"), trio->name.str(ctx) + "$invert_T");
+ replace_port(tbuf, ctx->id("E"), inv_lut.get(), ctx->id("A"));
+ inv_lut->params[ctx->id("INIT")] = "21845";
+ connect_ports(ctx, inv_lut.get(), ctx->id("Z"), trio, ctx->id("T"));
+ created_cells.push_back(std::move(inv_lut));
+
+ if (donet->users.size() > 1) {
+ for (auto user : donet->users)
+ log_info(" remaining tristate user: %s.%s\n", user.cell->name.c_str(ctx), user.port.c_str(ctx));
+ log_error("unsupported tristate IO pattern for IO buffer '%s', "
+ "instantiate SB_IO manually to ensure correct behaviour\n",
+ nxio->name.c_str(ctx));
+ }
+ ctx->nets.erase(donet->name);
+ todelete_cells.insert(tbuf->name);
+ }
+}
+
NEXTPNR_NAMESPACE_END
diff --git a/ecp5/cells.h b/ecp5/cells.h
index b0c74ca9..9c2ff3cf 100644
--- a/ecp5/cells.h
+++ b/ecp5/cells.h
@@ -48,6 +48,13 @@ inline bool is_l6mux(const BaseCtx *ctx, const CellInfo *cell) { return cell->ty
void ff_to_slice(Context *ctx, CellInfo *ff, CellInfo *lc, int index, bool driven_by_lut);
void lut_to_slice(Context *ctx, CellInfo *lut, CellInfo *lc, int index);
+void ccu2c_to_slice(Context *ctx, CellInfo *ccu, CellInfo *lc);
+void dram_to_ramw(Context *ctx, CellInfo *ram, CellInfo *lc);
+void dram_to_ram_slice(Context *ctx, CellInfo *ram, CellInfo *lc, CellInfo *ramw, int index);
+
+// Convert a nextpnr IO buffer to a TRELLIS_IO
+void nxio_to_tr(Context *ctx, CellInfo *nxio, CellInfo *trio, std::vector<std::unique_ptr<CellInfo>> &created_cells,
+ std::unordered_set<IdString> &todelete_cells);
NEXTPNR_NAMESPACE_END
diff --git a/ecp5/config.cc b/ecp5/config.cc
index 826c16a9..c8f94857 100644
--- a/ecp5/config.cc
+++ b/ecp5/config.cc
@@ -19,6 +19,7 @@
#include "config.h"
#include <boost/range/adaptor/reversed.hpp>
+#include <iomanip>
#include "log.h"
NEXTPNR_NAMESPACE_BEGIN
@@ -274,6 +275,28 @@ std::ostream &operator<<(std::ostream &out, const ChipConfig &cc)
out << std::endl;
}
}
+ for (const auto &bram : cc.bram_data) {
+ out << ".bram_init " << bram.first << std::endl;
+ std::ios_base::fmtflags f(out.flags());
+ for (size_t i = 0; i < bram.second.size(); i++) {
+ out << std::setw(3) << std::setfill('0') << std::hex << bram.second.at(i);
+ if (i % 8 == 7)
+ out << std::endl;
+ else
+ out << " ";
+ }
+ out.flags(f);
+ out << std::endl;
+ }
+ for (const auto &tg : cc.tilegroups) {
+ out << ".tile_group";
+ for (const auto &tile : tg.tiles) {
+ out << " " << tile;
+ }
+ out << std::endl;
+ out << tg.config;
+ out << std::endl;
+ }
return out;
}
@@ -294,6 +317,29 @@ std::istream &operator>>(std::istream &in, ChipConfig &cc)
TileConfig tc;
in >> tc;
cc.tiles[tilename] = tc;
+ } else if (verb == ".tile_group") {
+ TileGroup tg;
+ std::string line;
+ getline(in, line);
+ std::stringstream ss2(line);
+
+ std::string tile;
+ while (ss2) {
+ ss2 >> tile;
+ tg.tiles.push_back(tile);
+ }
+ in >> tg.config;
+ cc.tilegroups.push_back(tg);
+ } else if (verb == ".bram_init") {
+ uint16_t bram;
+ in >> bram;
+ std::ios_base::fmtflags f(in.flags());
+ while (!skip_check_eor(in)) {
+ uint16_t value;
+ in >> std::hex >> value;
+ cc.bram_data[bram].push_back(value);
+ }
+ in.flags(f);
} else {
log_error("unrecognised config entry %s\n", verb.c_str());
}
diff --git a/ecp5/config.h b/ecp5/config.h
index 3d2ef971..8b38de5d 100644
--- a/ecp5/config.h
+++ b/ecp5/config.h
@@ -98,6 +98,14 @@ std::ostream &operator<<(std::ostream &out, const TileConfig &tc);
std::istream &operator>>(std::istream &in, TileConfig &ce);
+// A group of tiles to configure at once for a particular feature that is split across tiles
+// TileGroups are currently for non-routing configuration only
+struct TileGroup
+{
+ std::vector<std::string> tiles;
+ TileConfig config;
+};
+
// This represents the configuration of a chip at a high level
class ChipConfig
{
@@ -105,6 +113,8 @@ class ChipConfig
std::string chip_name;
std::vector<std::string> metadata;
std::map<std::string, TileConfig> tiles;
+ std::vector<TileGroup> tilegroups;
+ std::map<uint16_t, std::vector<uint16_t>> bram_data;
};
std::ostream &operator<<(std::ostream &out, const ChipConfig &cc);
diff --git a/ecp5/constids.inc b/ecp5/constids.inc
index 12eb4a5a..bdcbc1ea 100644
--- a/ecp5/constids.inc
+++ b/ecp5/constids.inc
@@ -47,6 +47,766 @@ X(B)
X(TRELLIS_SLICE)
X(TRELLIS_IO)
+X(DCCA)
X(CLKMUX)
X(LSRMUX)
X(SRMODE)
+
+X(CLKI)
+X(CLKO)
+
+X(DP16KD)
+X(DIA0)
+X(DIA1)
+X(DIA2)
+X(DIA3)
+X(DIA4)
+X(DIA5)
+X(DIA6)
+X(DIA7)
+X(DIA8)
+X(DIA9)
+X(DIA10)
+X(DIA11)
+X(DIA12)
+X(DIA13)
+X(DIA14)
+X(DIA15)
+X(DIA16)
+X(DIA17)
+X(ADA0)
+X(ADA1)
+X(ADA2)
+X(ADA3)
+X(ADA4)
+X(ADA5)
+X(ADA6)
+X(ADA7)
+X(ADA8)
+X(ADA9)
+X(ADA10)
+X(ADA11)
+X(ADA12)
+X(ADA13)
+X(CEA)
+X(OCEA)
+X(CLKA)
+X(WEA)
+X(CSA2)
+X(CSA1)
+X(CSA0)
+X(RSTA)
+X(DIB0)
+X(DIB1)
+X(DIB2)
+X(DIB3)
+X(DIB4)
+X(DIB5)
+X(DIB6)
+X(DIB7)
+X(DIB8)
+X(DIB9)
+X(DIB10)
+X(DIB11)
+X(DIB12)
+X(DIB13)
+X(DIB14)
+X(DIB15)
+X(DIB16)
+X(DIB17)
+X(ADB0)
+X(ADB1)
+X(ADB2)
+X(ADB3)
+X(ADB4)
+X(ADB5)
+X(ADB6)
+X(ADB7)
+X(ADB8)
+X(ADB9)
+X(ADB10)
+X(ADB11)
+X(ADB12)
+X(ADB13)
+X(CEB)
+X(OCEB)
+X(CLKB)
+X(WEB)
+X(CSB2)
+X(CSB1)
+X(CSB0)
+X(RSTB)
+X(DOA0)
+X(DOA1)
+X(DOA2)
+X(DOA3)
+X(DOA4)
+X(DOA5)
+X(DOA6)
+X(DOA7)
+X(DOA8)
+X(DOA9)
+X(DOA10)
+X(DOA11)
+X(DOA12)
+X(DOA13)
+X(DOA14)
+X(DOA15)
+X(DOA16)
+X(DOA17)
+X(DOB0)
+X(DOB1)
+X(DOB2)
+X(DOB3)
+X(DOB4)
+X(DOB5)
+X(DOB6)
+X(DOB7)
+X(DOB8)
+X(DOB9)
+X(DOB10)
+X(DOB11)
+X(DOB12)
+X(DOB13)
+X(DOB14)
+X(DOB15)
+X(DOB16)
+X(DOB17)
+
+
+X(MULT18X18D)
+X(A2)
+X(A3)
+X(A4)
+X(A5)
+X(A6)
+X(A7)
+X(A8)
+X(A9)
+X(A10)
+X(A11)
+X(A12)
+X(A13)
+X(A14)
+X(A15)
+X(A16)
+X(A17)
+X(B2)
+X(B3)
+X(B4)
+X(B5)
+X(B6)
+X(B7)
+X(B8)
+X(B9)
+X(B10)
+X(B11)
+X(B12)
+X(B13)
+X(B14)
+X(B15)
+X(B16)
+X(B17)
+X(C2)
+X(C3)
+X(C4)
+X(C5)
+X(C6)
+X(C7)
+X(C8)
+X(C9)
+X(C10)
+X(C11)
+X(C12)
+X(C13)
+X(C14)
+X(C15)
+X(C16)
+X(C17)
+X(SIGNEDA)
+X(SIGNEDB)
+X(SOURCEA)
+X(SOURCEB)
+X(CLK0)
+X(CLK1)
+X(CLK2)
+X(CLK3)
+X(CE0)
+X(CE1)
+X(CE2)
+X(CE3)
+X(RST0)
+X(RST1)
+X(RST2)
+X(RST3)
+X(SRIA0)
+X(SRIA1)
+X(SRIA2)
+X(SRIA3)
+X(SRIA4)
+X(SRIA5)
+X(SRIA6)
+X(SRIA7)
+X(SRIA8)
+X(SRIA9)
+X(SRIA10)
+X(SRIA11)
+X(SRIA12)
+X(SRIA13)
+X(SRIA14)
+X(SRIA15)
+X(SRIA16)
+X(SRIA17)
+X(SRIB0)
+X(SRIB1)
+X(SRIB2)
+X(SRIB3)
+X(SRIB4)
+X(SRIB5)
+X(SRIB6)
+X(SRIB7)
+X(SRIB8)
+X(SRIB9)
+X(SRIB10)
+X(SRIB11)
+X(SRIB12)
+X(SRIB13)
+X(SRIB14)
+X(SRIB15)
+X(SRIB16)
+X(SRIB17)
+X(SROA0)
+X(SROA1)
+X(SROA2)
+X(SROA3)
+X(SROA4)
+X(SROA5)
+X(SROA6)
+X(SROA7)
+X(SROA8)
+X(SROA9)
+X(SROA10)
+X(SROA11)
+X(SROA12)
+X(SROA13)
+X(SROA14)
+X(SROA15)
+X(SROA16)
+X(SROA17)
+X(SROB0)
+X(SROB1)
+X(SROB2)
+X(SROB3)
+X(SROB4)
+X(SROB5)
+X(SROB6)
+X(SROB7)
+X(SROB8)
+X(SROB9)
+X(SROB10)
+X(SROB11)
+X(SROB12)
+X(SROB13)
+X(SROB14)
+X(SROB15)
+X(SROB16)
+X(SROB17)
+X(ROA0)
+X(ROA1)
+X(ROA2)
+X(ROA3)
+X(ROA4)
+X(ROA5)
+X(ROA6)
+X(ROA7)
+X(ROA8)
+X(ROA9)
+X(ROA10)
+X(ROA11)
+X(ROA12)
+X(ROA13)
+X(ROA14)
+X(ROA15)
+X(ROA16)
+X(ROA17)
+X(ROB0)
+X(ROB1)
+X(ROB2)
+X(ROB3)
+X(ROB4)
+X(ROB5)
+X(ROB6)
+X(ROB7)
+X(ROB8)
+X(ROB9)
+X(ROB10)
+X(ROB11)
+X(ROB12)
+X(ROB13)
+X(ROB14)
+X(ROB15)
+X(ROB16)
+X(ROB17)
+X(ROC0)
+X(ROC1)
+X(ROC2)
+X(ROC3)
+X(ROC4)
+X(ROC5)
+X(ROC6)
+X(ROC7)
+X(ROC8)
+X(ROC9)
+X(ROC10)
+X(ROC11)
+X(ROC12)
+X(ROC13)
+X(ROC14)
+X(ROC15)
+X(ROC16)
+X(ROC17)
+X(P0)
+X(P1)
+X(P2)
+X(P3)
+X(P4)
+X(P5)
+X(P6)
+X(P7)
+X(P8)
+X(P9)
+X(P10)
+X(P11)
+X(P12)
+X(P13)
+X(P14)
+X(P15)
+X(P16)
+X(P17)
+X(P18)
+X(P19)
+X(P20)
+X(P21)
+X(P22)
+X(P23)
+X(P24)
+X(P25)
+X(P26)
+X(P27)
+X(P28)
+X(P29)
+X(P30)
+X(P31)
+X(P32)
+X(P33)
+X(P34)
+X(P35)
+X(SIGNEDP)
+
+X(ALU54B)
+X(SIGNEDIA)
+X(SIGNEDIB)
+X(SIGNEDCIN)
+X(A18)
+X(A19)
+X(A20)
+X(A21)
+X(A22)
+X(A23)
+X(A24)
+X(A25)
+X(A26)
+X(A27)
+X(A28)
+X(A29)
+X(A30)
+X(A31)
+X(A32)
+X(A33)
+X(A34)
+X(A35)
+X(B18)
+X(B19)
+X(B20)
+X(B21)
+X(B22)
+X(B23)
+X(B24)
+X(B25)
+X(B26)
+X(B27)
+X(B28)
+X(B29)
+X(B30)
+X(B31)
+X(B32)
+X(B33)
+X(B34)
+X(B35)
+X(C18)
+X(C19)
+X(C20)
+X(C21)
+X(C22)
+X(C23)
+X(C24)
+X(C25)
+X(C26)
+X(C27)
+X(C28)
+X(C29)
+X(C30)
+X(C31)
+X(C32)
+X(C33)
+X(C34)
+X(C35)
+X(C36)
+X(C37)
+X(C38)
+X(C39)
+X(C40)
+X(C41)
+X(C42)
+X(C43)
+X(C44)
+X(C45)
+X(C46)
+X(C47)
+X(C48)
+X(C49)
+X(C50)
+X(C51)
+X(C52)
+X(C53)
+X(CFB0)
+X(CFB1)
+X(CFB2)
+X(CFB3)
+X(CFB4)
+X(CFB5)
+X(CFB6)
+X(CFB7)
+X(CFB8)
+X(CFB9)
+X(CFB10)
+X(CFB11)
+X(CFB12)
+X(CFB13)
+X(CFB14)
+X(CFB15)
+X(CFB16)
+X(CFB17)
+X(CFB18)
+X(CFB19)
+X(CFB20)
+X(CFB21)
+X(CFB22)
+X(CFB23)
+X(CFB24)
+X(CFB25)
+X(CFB26)
+X(CFB27)
+X(CFB28)
+X(CFB29)
+X(CFB30)
+X(CFB31)
+X(CFB32)
+X(CFB33)
+X(CFB34)
+X(CFB35)
+X(CFB36)
+X(CFB37)
+X(CFB38)
+X(CFB39)
+X(CFB40)
+X(CFB41)
+X(CFB42)
+X(CFB43)
+X(CFB44)
+X(CFB45)
+X(CFB46)
+X(CFB47)
+X(CFB48)
+X(CFB49)
+X(CFB50)
+X(CFB51)
+X(CFB52)
+X(CFB53)
+X(MA0)
+X(MA1)
+X(MA2)
+X(MA3)
+X(MA4)
+X(MA5)
+X(MA6)
+X(MA7)
+X(MA8)
+X(MA9)
+X(MA10)
+X(MA11)
+X(MA12)
+X(MA13)
+X(MA14)
+X(MA15)
+X(MA16)
+X(MA17)
+X(MA18)
+X(MA19)
+X(MA20)
+X(MA21)
+X(MA22)
+X(MA23)
+X(MA24)
+X(MA25)
+X(MA26)
+X(MA27)
+X(MA28)
+X(MA29)
+X(MA30)
+X(MA31)
+X(MA32)
+X(MA33)
+X(MA34)
+X(MA35)
+X(MB0)
+X(MB1)
+X(MB2)
+X(MB3)
+X(MB4)
+X(MB5)
+X(MB6)
+X(MB7)
+X(MB8)
+X(MB9)
+X(MB10)
+X(MB11)
+X(MB12)
+X(MB13)
+X(MB14)
+X(MB15)
+X(MB16)
+X(MB17)
+X(MB18)
+X(MB19)
+X(MB20)
+X(MB21)
+X(MB22)
+X(MB23)
+X(MB24)
+X(MB25)
+X(MB26)
+X(MB27)
+X(MB28)
+X(MB29)
+X(MB30)
+X(MB31)
+X(MB32)
+X(MB33)
+X(MB34)
+X(MB35)
+X(CIN0)
+X(CIN1)
+X(CIN2)
+X(CIN3)
+X(CIN4)
+X(CIN5)
+X(CIN6)
+X(CIN7)
+X(CIN8)
+X(CIN9)
+X(CIN10)
+X(CIN11)
+X(CIN12)
+X(CIN13)
+X(CIN14)
+X(CIN15)
+X(CIN16)
+X(CIN17)
+X(CIN18)
+X(CIN19)
+X(CIN20)
+X(CIN21)
+X(CIN22)
+X(CIN23)
+X(CIN24)
+X(CIN25)
+X(CIN26)
+X(CIN27)
+X(CIN28)
+X(CIN29)
+X(CIN30)
+X(CIN31)
+X(CIN32)
+X(CIN33)
+X(CIN34)
+X(CIN35)
+X(CIN36)
+X(CIN37)
+X(CIN38)
+X(CIN39)
+X(CIN40)
+X(CIN41)
+X(CIN42)
+X(CIN43)
+X(CIN44)
+X(CIN45)
+X(CIN46)
+X(CIN47)
+X(CIN48)
+X(CIN49)
+X(CIN50)
+X(CIN51)
+X(CIN52)
+X(CIN53)
+X(OP0)
+X(OP1)
+X(OP2)
+X(OP3)
+X(OP4)
+X(OP5)
+X(OP6)
+X(OP7)
+X(OP8)
+X(OP9)
+X(OP10)
+X(R0)
+X(R1)
+X(R2)
+X(R3)
+X(R4)
+X(R5)
+X(R6)
+X(R7)
+X(R8)
+X(R9)
+X(R10)
+X(R11)
+X(R12)
+X(R13)
+X(R14)
+X(R15)
+X(R16)
+X(R17)
+X(R18)
+X(R19)
+X(R20)
+X(R21)
+X(R22)
+X(R23)
+X(R24)
+X(R25)
+X(R26)
+X(R27)
+X(R28)
+X(R29)
+X(R30)
+X(R31)
+X(R32)
+X(R33)
+X(R34)
+X(R35)
+X(R36)
+X(R37)
+X(R38)
+X(R39)
+X(R40)
+X(R41)
+X(R42)
+X(R43)
+X(R44)
+X(R45)
+X(R46)
+X(R47)
+X(R48)
+X(R49)
+X(R50)
+X(R51)
+X(R52)
+X(R53)
+X(CO0)
+X(CO1)
+X(CO2)
+X(CO3)
+X(CO4)
+X(CO5)
+X(CO6)
+X(CO7)
+X(CO8)
+X(CO9)
+X(CO10)
+X(CO11)
+X(CO12)
+X(CO13)
+X(CO14)
+X(CO15)
+X(CO16)
+X(CO17)
+X(CO18)
+X(CO19)
+X(CO20)
+X(CO21)
+X(CO22)
+X(CO23)
+X(CO24)
+X(CO25)
+X(CO26)
+X(CO27)
+X(CO28)
+X(CO29)
+X(CO30)
+X(CO31)
+X(CO32)
+X(CO33)
+X(CO34)
+X(CO35)
+X(CO36)
+X(CO37)
+X(CO38)
+X(CO39)
+X(CO40)
+X(CO41)
+X(CO42)
+X(CO43)
+X(CO44)
+X(CO45)
+X(CO46)
+X(CO47)
+X(CO48)
+X(CO49)
+X(CO50)
+X(CO51)
+X(CO52)
+X(CO53)
+X(EQZ)
+X(EQZM)
+X(EQOM)
+X(EQPAT)
+X(EQPATB)
+X(OVER)
+X(UNDER)
+X(OVERUNDER)
+X(SIGNEDR)
+
+X(EHXPLLL)
+X(CLKFB)
+X(PHASESEL1)
+X(PHASESEL0)
+X(PHASEDIR)
+X(PHASESTEP)
+X(PHASELOADREG)
+X(STDBY)
+X(PLLWAKESYNC)
+X(RST)
+X(ENCLKOP)
+X(ENCLKOS)
+X(ENCLKOS2)
+X(ENCLKOS3)
+X(CLKOP)
+X(CLKOS)
+X(CLKOS2)
+X(CLKOS3)
+X(LOCK)
+X(INTLOCK)
+X(REFCLK)
+X(CLKINTFB)
diff --git a/ecp5/globals.cc b/ecp5/globals.cc
new file mode 100644
index 00000000..06412fef
--- /dev/null
+++ b/ecp5/globals.cc
@@ -0,0 +1,426 @@
+/*
+ * nextpnr -- Next Generation Place and Route
+ *
+ * Copyright (C) 2018 David Shah <david@symbioticeda.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "globals.h"
+#include <algorithm>
+#include <iomanip>
+#include <queue>
+#include "cells.h"
+#include "log.h"
+#include "nextpnr.h"
+#include "place_common.h"
+#include "util.h"
+#define fmt_str(x) (static_cast<const std::ostringstream &>(std::ostringstream() << x).str())
+
+NEXTPNR_NAMESPACE_BEGIN
+
+static std::string get_quad_name(GlobalQuadrant quad)
+{
+ switch (quad) {
+ case QUAD_UL:
+ return "UL";
+ case QUAD_UR:
+ return "UR";
+ case QUAD_LL:
+ return "LL";
+ case QUAD_LR:
+ return "LR";
+ }
+ return "";
+}
+
+class Ecp5GlobalRouter
+{
+ public:
+ Ecp5GlobalRouter(Context *ctx) : ctx(ctx){};
+
+ private:
+ bool is_clock_port(const PortRef &user)
+ {
+ if (user.cell->type == id_TRELLIS_SLICE && (user.port == id_CLK || user.port == id_WCK))
+ return true;
+ return false;
+ }
+
+ std::vector<NetInfo *> get_clocks()
+ {
+ std::unordered_map<IdString, int> clockCount;
+ for (auto &net : ctx->nets) {
+ NetInfo *ni = net.second.get();
+ clockCount[ni->name] = 0;
+ for (const auto &user : ni->users) {
+ if (is_clock_port(user))
+ clockCount[ni->name]++;
+ }
+ // log_info("clkcount %s: %d\n", ni->name.c_str(ctx),clockCount[ni->name]);
+ }
+ std::vector<NetInfo *> clocks;
+ while (clocks.size() < 16) {
+ auto max = std::max_element(clockCount.begin(), clockCount.end(),
+ [](const decltype(clockCount)::value_type &a,
+ const decltype(clockCount)::value_type &b) { return a.second < b.second; });
+ if (max == clockCount.end() || max->second < 5)
+ break;
+ clocks.push_back(ctx->nets.at(max->first).get());
+ clockCount.erase(max->first);
+ }
+ return clocks;
+ }
+
+ PipId find_tap_pip(WireId tile_glb)
+ {
+ std::string wireName = ctx->getWireBasename(tile_glb).str(ctx);
+ std::string glbName = wireName.substr(2);
+ TapDirection td = ctx->globalInfoAtLoc(tile_glb.location).tap_dir;
+ WireId tap_wire;
+ Location tap_loc;
+ tap_loc.x = ctx->globalInfoAtLoc(tile_glb.location).tap_col;
+ tap_loc.y = tile_glb.location.y;
+ if (td == TAP_DIR_LEFT) {
+ tap_wire = ctx->getWireByLocAndBasename(tap_loc, "L_" + glbName);
+ } else {
+ tap_wire = ctx->getWireByLocAndBasename(tap_loc, "R_" + glbName);
+ }
+ NPNR_ASSERT(tap_wire != WireId());
+ return *(ctx->getPipsUphill(tap_wire).begin());
+ }
+
+ PipId find_spine_pip(WireId tap_wire)
+ {
+ std::string wireName = ctx->getWireBasename(tap_wire).str(ctx);
+ Location spine_loc;
+ spine_loc.x = ctx->globalInfoAtLoc(tap_wire.location).spine_col;
+ spine_loc.y = ctx->globalInfoAtLoc(tap_wire.location).spine_row;
+ WireId spine_wire = ctx->getWireByLocAndBasename(spine_loc, wireName);
+ return *(ctx->getPipsUphill(spine_wire).begin());
+ }
+
+ void route_logic_tile_global(NetInfo *net, int global_index, PortRef user)
+ {
+ WireId userWire = ctx->getBelPinWire(user.cell->bel, user.port);
+ WireId globalWire;
+ IdString global_name = ctx->id(fmt_str("G_HPBX" << std::setw(2) << std::setfill('0') << global_index << "00"));
+ std::queue<WireId> upstream;
+ std::unordered_map<WireId, PipId> backtrace;
+ upstream.push(userWire);
+ bool already_routed = false;
+ WireId next;
+ // Search back from the pin until we reach the global network
+ while (true) {
+ next = upstream.front();
+ upstream.pop();
+
+ if (ctx->getBoundWireNet(next) == net) {
+ already_routed = true;
+ globalWire = next;
+ break;
+ }
+
+ if (ctx->getWireBasename(next) == global_name) {
+ globalWire = next;
+ break;
+ }
+ if (ctx->checkWireAvail(next)) {
+ for (auto pip : ctx->getPipsUphill(next)) {
+ WireId src = ctx->getPipSrcWire(pip);
+ backtrace[src] = pip;
+ upstream.push(src);
+ }
+ }
+ if (upstream.size() > 30000) {
+ log_error("failed to route HPBX%02d00 to %s.%s\n", global_index,
+ ctx->getBelName(user.cell->bel).c_str(ctx), user.port.c_str(ctx));
+ }
+ }
+ // Set all the pips we found along the way
+ WireId cursor = next;
+ while (true) {
+ auto fnd = backtrace.find(cursor);
+ if (fnd == backtrace.end())
+ break;
+ ctx->bindPip(fnd->second, net, STRENGTH_LOCKED);
+ cursor = ctx->getPipDstWire(fnd->second);
+ }
+ // If the global network inside the tile isn't already set up,
+ // we also need to bind the buffers along the way
+ if (!already_routed) {
+ ctx->bindWire(next, net, STRENGTH_LOCKED);
+ PipId tap_pip = find_tap_pip(next);
+ NetInfo *tap_net = ctx->getBoundPipNet(tap_pip);
+ if (tap_net == nullptr) {
+ ctx->bindPip(tap_pip, net, STRENGTH_LOCKED);
+ PipId spine_pip = find_spine_pip(ctx->getPipSrcWire(tap_pip));
+ NetInfo *spine_net = ctx->getBoundPipNet(spine_pip);
+ if (spine_net == nullptr) {
+ ctx->bindPip(spine_pip, net, STRENGTH_LOCKED);
+ } else {
+ NPNR_ASSERT(spine_net == net);
+ }
+ } else {
+ NPNR_ASSERT(tap_net == net);
+ }
+ }
+ }
+
+ bool is_global_io(CellInfo *io, std::string &glb_name)
+ {
+ std::string func_name = ctx->getPioFunctionName(io->bel);
+ if (func_name.substr(0, 5) == "PCLKT") {
+ func_name.erase(func_name.find('_'), 1);
+ glb_name = "G_" + func_name;
+ return true;
+ }
+ return false;
+ }
+
+ WireId get_global_wire(GlobalQuadrant quad, int network)
+ {
+ return ctx->getWireByLocAndBasename(Location(0, 0),
+ "G_" + get_quad_name(quad) + "PCLK" + std::to_string(network));
+ }
+
+ bool simple_router(NetInfo *net, WireId src, WireId dst, bool allow_fail = false)
+ {
+ std::queue<WireId> visit;
+ std::unordered_map<WireId, PipId> backtrace;
+ visit.push(src);
+ WireId cursor;
+ while (true) {
+
+ if (visit.empty() || visit.size() > 50000) {
+ if (allow_fail)
+ return false;
+ log_error("cannot route global from %s to %s.\n", ctx->getWireName(src).c_str(ctx),
+ ctx->getWireName(dst).c_str(ctx));
+ }
+ cursor = visit.front();
+ visit.pop();
+ NetInfo *bound = ctx->getBoundWireNet(cursor);
+ if (bound == net) {
+ } else if (bound != nullptr) {
+ continue;
+ }
+ if (cursor == dst)
+ break;
+ for (auto dh : ctx->getPipsDownhill(cursor)) {
+ WireId pipDst = ctx->getPipDstWire(dh);
+ if (backtrace.count(pipDst))
+ continue;
+ backtrace[pipDst] = dh;
+ visit.push(pipDst);
+ }
+ }
+ while (true) {
+ auto fnd = backtrace.find(cursor);
+ if (fnd == backtrace.end())
+ break;
+ NetInfo *bound = ctx->getBoundWireNet(cursor);
+ if (bound != nullptr) {
+ NPNR_ASSERT(bound == net);
+ break;
+ }
+ ctx->bindPip(fnd->second, net, STRENGTH_LOCKED);
+ cursor = ctx->getPipSrcWire(fnd->second);
+ }
+ if (ctx->getBoundWireNet(src) == nullptr)
+ ctx->bindWire(src, net, STRENGTH_LOCKED);
+ return true;
+ }
+
+ bool route_onto_global(NetInfo *net, int network)
+ {
+ WireId glb_src;
+ NPNR_ASSERT(net->driver.cell->type == id_DCCA);
+ glb_src = ctx->getNetinfoSourceWire(net);
+ for (int quad = QUAD_UL; quad < QUAD_LR + 1; quad++) {
+ WireId glb_dst = get_global_wire(GlobalQuadrant(quad), network);
+ NPNR_ASSERT(glb_dst != WireId());
+ bool routed = simple_router(net, glb_src, glb_dst);
+ if (!routed)
+ return false;
+ }
+ return true;
+ }
+
+ // Get DCC wirelength based on source
+ wirelen_t get_dcc_wirelen(CellInfo *dcc)
+ {
+ NetInfo *clki = dcc->ports.at(id_CLKI).net;
+ BelId drv_bel;
+ const PortRef &drv = clki->driver;
+ if (drv.cell == nullptr) {
+ return 0;
+ } else if (drv.cell->attrs.count(ctx->id("BEL"))) {
+ drv_bel = ctx->getBelByName(ctx->id(drv.cell->attrs.at(ctx->id("BEL"))));
+ } else {
+ // Check if driver is a singleton
+ BelId last_bel;
+ bool singleton = true;
+ for (auto bel : ctx->getBels()) {
+ if (ctx->getBelType(bel) == drv.cell->type) {
+ if (last_bel != BelId()) {
+ singleton = false;
+ break;
+ }
+ last_bel = bel;
+ }
+ }
+ if (singleton && last_bel != BelId()) {
+ drv_bel = last_bel;
+ }
+ }
+ if (drv_bel == BelId()) {
+ // Driver is not locked. Use standard metric
+ float tns;
+ return get_net_metric(ctx, clki, MetricType::WIRELENGTH, tns);
+ } else {
+ // Driver is locked
+ Loc dcc_loc = ctx->getBelLocation(dcc->bel);
+ Loc drv_loc = ctx->getBelLocation(drv_bel);
+ return std::abs(dcc_loc.x - drv_loc.x) + std::abs(dcc_loc.y - drv_loc.y);
+ }
+ }
+
+ // Attempt to place a DCC
+ void place_dcc(CellInfo *dcc)
+ {
+ BelId best_bel;
+ wirelen_t best_wirelen = 9999999;
+ for (auto bel : ctx->getBels()) {
+ if (ctx->getBelType(bel) == id_DCCA && ctx->checkBelAvail(bel)) {
+ if (ctx->isValidBelForCell(dcc, bel)) {
+ ctx->bindBel(bel, dcc, STRENGTH_LOCKED);
+ wirelen_t wirelen = get_dcc_wirelen(dcc);
+ if (wirelen < best_wirelen) {
+ best_bel = bel;
+ best_wirelen = wirelen;
+ }
+ ctx->unbindBel(bel);
+ }
+ }
+ }
+ NPNR_ASSERT(best_bel != BelId());
+ ctx->bindBel(best_bel, dcc, STRENGTH_LOCKED);
+ }
+
+ // Insert a DCC into a net to promote it to a global
+ NetInfo *insert_dcc(NetInfo *net)
+ {
+ auto dcc = create_ecp5_cell(ctx, id_DCCA, "$gbuf$" + net->name.str(ctx));
+
+ std::unique_ptr<NetInfo> glbnet = std::unique_ptr<NetInfo>(new NetInfo);
+ glbnet->name = ctx->id("$glbnet$" + net->name.str(ctx));
+ glbnet->driver.cell = dcc.get();
+ glbnet->driver.port = id_CLKO;
+ glbnet->is_global = true;
+ dcc->ports[id_CLKO].net = glbnet.get();
+
+ std::vector<PortRef> keep_users;
+ for (auto user : net->users) {
+ if (user.port == id_CLKFB) {
+ keep_users.push_back(user);
+ } else {
+ glbnet->users.push_back(user);
+ user.cell->ports.at(user.port).net = glbnet.get();
+ }
+ }
+ net->users = keep_users;
+
+ dcc->ports[id_CLKI].net = net;
+ PortRef clki_pr;
+ clki_pr.port = id_CLKI;
+ clki_pr.cell = dcc.get();
+ net->users.push_back(clki_pr);
+
+ place_dcc(dcc.get());
+
+ ctx->cells[dcc->name] = std::move(dcc);
+ NetInfo *glbptr = glbnet.get();
+ ctx->nets[glbnet->name] = std::move(glbnet);
+ return glbptr;
+ }
+
+ int global_route_priority(const PortRef &load)
+ {
+ if (load.port == id_WCK || load.port == id_WRE)
+ return 90;
+ return 99;
+ }
+
+ Context *ctx;
+
+ public:
+ void promote_globals()
+ {
+ log_info("Promoting globals...\n");
+ auto clocks = get_clocks();
+ for (auto clock : clocks) {
+ log_info(" promoting clock net %s to global network\n", clock->name.c_str(ctx));
+ insert_dcc(clock);
+ }
+ }
+
+ void route_globals()
+ {
+ log_info("Routing globals...\n");
+ std::set<int> all_globals, fab_globals;
+ for (int i = 0; i < 16; i++) {
+ all_globals.insert(i);
+ if (i < 8)
+ fab_globals.insert(i);
+ }
+ for (auto cell : sorted(ctx->cells)) {
+ CellInfo *ci = cell.second;
+ if (ci->type == id_DCCA) {
+ NetInfo *clock = ci->ports.at(id_CLKO).net;
+ NPNR_ASSERT(clock != nullptr);
+ bool drives_fabric = std::any_of(clock->users.begin(), clock->users.end(),
+ [this](const PortRef &port) { return !is_clock_port(port); });
+
+ int glbid;
+ if (drives_fabric) {
+ if (fab_globals.empty())
+ continue;
+ glbid = *(fab_globals.begin());
+ } else {
+ glbid = *(all_globals.begin());
+ }
+ all_globals.erase(glbid);
+ fab_globals.erase(glbid);
+
+ log_info(" routing clock net %s using global %d\n", clock->name.c_str(ctx), glbid);
+ bool routed = route_onto_global(clock, glbid);
+ NPNR_ASSERT(routed);
+
+ // WCK must have routing priority
+ auto sorted_users = clock->users;
+ std::sort(sorted_users.begin(), sorted_users.end(), [this](const PortRef &a, const PortRef &b) {
+ return global_route_priority(a) < global_route_priority(b);
+ });
+ for (const auto &user : sorted_users) {
+ route_logic_tile_global(clock, glbid, user);
+ }
+ }
+ }
+ }
+};
+void promote_ecp5_globals(Context *ctx) { Ecp5GlobalRouter(ctx).promote_globals(); }
+void route_ecp5_globals(Context *ctx) { Ecp5GlobalRouter(ctx).route_globals(); }
+
+NEXTPNR_NAMESPACE_END
diff --git a/ecp5/globals.h b/ecp5/globals.h
new file mode 100644
index 00000000..cc7cf98e
--- /dev/null
+++ b/ecp5/globals.h
@@ -0,0 +1,27 @@
+/*
+ * nextpnr -- Next Generation Place and Route
+ *
+ * Copyright (C) 2018 David Shah <david@symbioticeda.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "nextpnr.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+void promote_ecp5_globals(Context *ctx);
+void route_ecp5_globals(Context *ctx);
+
+NEXTPNR_NAMESPACE_END \ No newline at end of file
diff --git a/ecp5/lpf.cc b/ecp5/lpf.cc
new file mode 100644
index 00000000..4bde660e
--- /dev/null
+++ b/ecp5/lpf.cc
@@ -0,0 +1,106 @@
+/*
+ * nextpnr -- Next Generation Place and Route
+ *
+ * Copyright (C) 2018 David Shah <david@symbioticeda.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include <sstream>
+#include "log.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+bool Arch::applyLPF(std::string filename, std::istream &in)
+{
+ auto isempty = [](const std::string &str) {
+ return std::all_of(str.begin(), str.end(), [](char c) { return isblank(c); });
+ };
+ auto strip_quotes = [](const std::string &str) {
+ if (str.at(0) == '"') {
+ NPNR_ASSERT(str.back() == '"');
+ return str.substr(1, str.size() - 2);
+ } else {
+ return str;
+ }
+ };
+
+ try {
+ if (!in)
+ log_error("failed to open LPF file\n");
+ std::string line;
+ std::string linebuf;
+ while (std::getline(in, line)) {
+ size_t cstart = line.find('#');
+ if (cstart != std::string::npos)
+ line = line.substr(0, cstart);
+ if (isempty(line))
+ continue;
+ linebuf += line;
+ // Look for a command up to a semicolon
+ size_t scpos = linebuf.find(';');
+ while (scpos != std::string::npos) {
+ std::string command = linebuf.substr(0, scpos);
+ // Split command into words
+ std::stringstream ss(command);
+ std::vector<std::string> words;
+ std::string tmp;
+ while (ss >> tmp)
+ words.push_back(tmp);
+ if (words.size() >= 0) {
+ std::string verb = words.at(0);
+ if (verb == "BLOCK" || verb == "SYSCONFIG" || verb == "FREQUENCY") {
+ log_warning(" ignoring unsupported LPF command '%s'\n", command.c_str());
+ } else if (verb == "LOCATE") {
+ NPNR_ASSERT(words.at(1) == "COMP");
+ std::string cell = strip_quotes(words.at(2));
+ NPNR_ASSERT(words.at(3) == "SITE");
+ auto fnd_cell = cells.find(id(cell));
+ if (fnd_cell == cells.end()) {
+ log_warning("unmatched LPF 'LOCATE COMP' '%s'\n", cell.c_str());
+ } else {
+ fnd_cell->second->attrs[id("LOC")] = strip_quotes(words.at(4));
+ }
+ } else if (verb == "IOBUF") {
+ NPNR_ASSERT(words.at(1) == "PORT");
+ std::string cell = strip_quotes(words.at(2));
+ auto fnd_cell = cells.find(id(cell));
+ if (fnd_cell == cells.end()) {
+ log_warning("unmatched LPF 'IOBUF PORT' '%s'\n", cell.c_str());
+ } else {
+ for (size_t i = 3; i < words.size(); i++) {
+ std::string setting = words.at(i);
+ size_t eqpos = setting.find('=');
+ NPNR_ASSERT(eqpos != std::string::npos);
+ std::string key = setting.substr(0, eqpos), value = setting.substr(eqpos + 1);
+ fnd_cell->second->attrs[id(key)] = value;
+ }
+ }
+ }
+ }
+
+ linebuf = linebuf.substr(scpos + 1);
+ scpos = linebuf.find(';');
+ }
+ }
+ if (!isempty(linebuf))
+ log_error("unexpected end of LPF file\n");
+ settings.emplace(id("input/lpf"), filename);
+ return true;
+ } catch (log_execution_error_exception) {
+ return false;
+ }
+}
+
+NEXTPNR_NAMESPACE_END
diff --git a/ecp5/main.cc b/ecp5/main.cc
index 5ad5a9bf..c444f96f 100644
--- a/ecp5/main.cc
+++ b/ecp5/main.cc
@@ -35,6 +35,7 @@ class ECP5CommandHandler : public CommandHandler
virtual ~ECP5CommandHandler(){};
std::unique_ptr<Context> createContext() override;
void setupArchContext(Context *ctx) override{};
+ void customAfterLoad(Context *ctx) override;
void validate() override;
void customBitstream(Context *ctx) override;
@@ -50,9 +51,19 @@ po::options_description ECP5CommandHandler::getArchOptions()
specific.add_options()("25k", "set device type to LFE5U-25F");
specific.add_options()("45k", "set device type to LFE5U-45F");
specific.add_options()("85k", "set device type to LFE5U-85F");
+ specific.add_options()("um-25k", "set device type to LFE5UM-25F");
+ specific.add_options()("um-45k", "set device type to LFE5UM-45F");
+ specific.add_options()("um-85k", "set device type to LFE5UM-85F");
+ specific.add_options()("um5g-25k", "set device type to LFE5UM5G-25F");
+ specific.add_options()("um5g-45k", "set device type to LFE5UM5G-45F");
+ specific.add_options()("um5g-85k", "set device type to LFE5UM5G-85F");
+
specific.add_options()("package", po::value<std::string>(), "select device package (defaults to CABGA381)");
specific.add_options()("basecfg", po::value<std::string>(), "base chip configuration in Trellis text format");
specific.add_options()("textcfg", po::value<std::string>(), "textual configuration in Trellis format to write");
+
+ specific.add_options()("lpf", po::value<std::vector<std::string>>(), "LPF pin constraint file(s)");
+
return specific;
}
void ECP5CommandHandler::validate()
@@ -84,6 +95,18 @@ std::unique_ptr<Context> ECP5CommandHandler::createContext()
chipArgs.type = ArchArgs::LFE5U_45F;
if (vm.count("85k"))
chipArgs.type = ArchArgs::LFE5U_85F;
+ if (vm.count("um-25k"))
+ chipArgs.type = ArchArgs::LFE5UM_25F;
+ if (vm.count("um-45k"))
+ chipArgs.type = ArchArgs::LFE5UM_45F;
+ if (vm.count("um-85k"))
+ chipArgs.type = ArchArgs::LFE5UM_85F;
+ if (vm.count("um5g-25k"))
+ chipArgs.type = ArchArgs::LFE5UM5G_25F;
+ if (vm.count("um5g-45k"))
+ chipArgs.type = ArchArgs::LFE5UM5G_45F;
+ if (vm.count("um5g-85k"))
+ chipArgs.type = ArchArgs::LFE5UM5G_85F;
if (vm.count("package"))
chipArgs.package = vm["package"].as<std::string>();
else
@@ -93,6 +116,17 @@ std::unique_ptr<Context> ECP5CommandHandler::createContext()
return std::unique_ptr<Context>(new Context(chipArgs));
}
+void ECP5CommandHandler::customAfterLoad(Context *ctx)
+{
+ if (vm.count("lpf")) {
+ std::vector<std::string> files = vm["lpf"].as<std::vector<std::string>>();
+ for (const auto &filename : files) {
+ std::ifstream in(filename);
+ ctx->applyLPF(filename, in);
+ }
+ }
+}
+
int main(int argc, char *argv[])
{
ECP5CommandHandler handler(argc, argv);
diff --git a/ecp5/pack.cc b/ecp5/pack.cc
index a2077204..73e15609 100644
--- a/ecp5/pack.cc
+++ b/ecp5/pack.cc
@@ -18,13 +18,15 @@
*/
#include <algorithm>
+#include <boost/optional.hpp>
#include <iterator>
#include <unordered_set>
#include "cells.h"
+#include "chain_utils.h"
#include "design_utils.h"
+#include "globals.h"
#include "log.h"
#include "util.h"
-
NEXTPNR_NAMESPACE_BEGIN
static bool is_nextpnr_iob(Context *ctx, CellInfo *cell)
@@ -106,6 +108,41 @@ class Ecp5Packer
return true;
}
+ // Return whether or not an FF can be added to a tile (pairing checks must also be done using the fn above)
+ bool can_add_ff_to_tile(const std::vector<CellInfo *> &tile_ffs, CellInfo *ff0)
+ {
+ for (const auto &existing : tile_ffs) {
+ if (net_or_nullptr(existing, ctx->id("CLK")) != net_or_nullptr(ff0, ctx->id("CLK")))
+ return false;
+ if (net_or_nullptr(existing, ctx->id("LSR")) != net_or_nullptr(ff0, ctx->id("LSR")))
+ return false;
+ if (str_or_default(existing->params, ctx->id("CLKMUX"), "CLK") !=
+ str_or_default(ff0->params, ctx->id("CLKMUX"), "CLK"))
+ return false;
+ if (str_or_default(existing->params, ctx->id("LSRMUX"), "LSR") !=
+ str_or_default(ff0->params, ctx->id("LSRMUX"), "LSR"))
+ return false;
+ if (str_or_default(existing->params, ctx->id("SRMODE"), "LSR_OVER_CE") !=
+ str_or_default(ff0->params, ctx->id("SRMODE"), "LSR_OVER_CE"))
+ return false;
+ }
+ return true;
+ }
+
+ // Return true if a FF can be added to a DPRAM slice
+ bool can_pack_ff_dram(CellInfo *dpram, CellInfo *ff)
+ {
+ std::string wckmux = str_or_default(dpram->params, ctx->id("WCKMUX"), "WCK");
+ std::string clkmux = str_or_default(ff->params, ctx->id("CLKMUX"), "CLK");
+ if (wckmux != clkmux && !(wckmux == "WCK" && clkmux == "CLK"))
+ return false;
+ std::string wremux = str_or_default(dpram->params, ctx->id("WREMUX"), "WRE");
+ std::string lsrmux = str_or_default(ff->params, ctx->id("LSRMUX"), "LSR");
+ if (wremux != lsrmux && !(wremux == "WRE" && lsrmux == "LSR"))
+ return false;
+ return true;
+ }
+
// Return true if two LUTs can be paired considering FF compatibility
bool can_pack_lutff(IdString lut0, IdString lut1)
{
@@ -230,11 +267,17 @@ class Ecp5Packer
}
}
} else {
- log_error("TRELLIS_IO required on all top level IOs...\n");
+ // Create a TRELLIS_IO buffer
+ std::unique_ptr<CellInfo> tr_cell =
+ create_ecp5_cell(ctx, ctx->id("TRELLIS_IO"), ci->name.str(ctx) + "$tr_io");
+ nxio_to_tr(ctx, ci, tr_cell.get(), new_cells, packed_cells);
+ new_cells.push_back(std::move(tr_cell));
+ trio = new_cells.back().get();
}
packed_cells.insert(ci->name);
- std::copy(ci->attrs.begin(), ci->attrs.end(), std::inserter(trio->attrs, trio->attrs.begin()));
+ for (const auto &attr : ci->attrs)
+ trio->attrs[attr.first] = attr.second;
auto loc_attr = trio->attrs.find(ctx->id("LOC"));
if (loc_attr != trio->attrs.end()) {
@@ -312,6 +355,323 @@ class Ecp5Packer
flush_cells();
}
+ // Create a feed in to the carry chain
+ CellInfo *make_carry_feed_in(NetInfo *carry, PortRef chain_in)
+ {
+ std::unique_ptr<CellInfo> feedin = create_ecp5_cell(ctx, ctx->id("CCU2C"));
+
+ feedin->params[ctx->id("INIT0")] = "10"; // LUT4 = 0; LUT2 = A
+ feedin->params[ctx->id("INIT1")] = "65535";
+ feedin->params[ctx->id("INJECT1_0")] = "NO";
+ feedin->params[ctx->id("INJECT1_1")] = "YES";
+
+ carry->users.erase(std::remove_if(carry->users.begin(), carry->users.end(),
+ [chain_in](const PortRef &user) {
+ return user.port == chain_in.port && user.cell == chain_in.cell;
+ }),
+ carry->users.end());
+ connect_port(ctx, carry, feedin.get(), id_A0);
+
+ std::unique_ptr<NetInfo> new_carry(new NetInfo());
+ new_carry->name = ctx->id(feedin->name.str(ctx) + "$COUT");
+ connect_port(ctx, new_carry.get(), feedin.get(), ctx->id("COUT"));
+ chain_in.cell->ports[chain_in.port].net = nullptr;
+ connect_port(ctx, new_carry.get(), chain_in.cell, chain_in.port);
+
+ CellInfo *feedin_ptr = feedin.get();
+ IdString feedin_name = feedin->name;
+ ctx->cells[feedin_name] = std::move(feedin);
+ IdString new_carry_name = new_carry->name;
+ ctx->nets[new_carry_name] = std::move(new_carry);
+ return feedin_ptr;
+ }
+
+ // Create a feed out and loop through from the carry chain
+ CellInfo *make_carry_feed_out(NetInfo *carry, boost::optional<PortRef> chain_next = boost::optional<PortRef>())
+ {
+ std::unique_ptr<CellInfo> feedout = create_ecp5_cell(ctx, ctx->id("CCU2C"));
+ feedout->params[ctx->id("INIT0")] = "0";
+ feedout->params[ctx->id("INIT1")] = "10"; // LUT4 = 0; LUT2 = A
+ feedout->params[ctx->id("INJECT1_0")] = "NO";
+ feedout->params[ctx->id("INJECT1_1")] = "NO";
+
+ PortRef carry_drv = carry->driver;
+ carry->driver.cell = nullptr;
+ connect_port(ctx, carry, feedout.get(), ctx->id("S0"));
+
+ std::unique_ptr<NetInfo> new_cin(new NetInfo());
+ new_cin->name = ctx->id(feedout->name.str(ctx) + "$CIN");
+ new_cin->driver = carry_drv;
+ carry_drv.cell->ports.at(carry_drv.port).net = new_cin.get();
+ connect_port(ctx, new_cin.get(), feedout.get(), ctx->id("CIN"));
+
+ if (chain_next) {
+ // Loop back into LUT4_1 for feedthrough
+ connect_port(ctx, carry, feedout.get(), id_A1);
+
+ carry->users.erase(std::remove_if(carry->users.begin(), carry->users.end(),
+ [chain_next](const PortRef &user) {
+ return user.port == chain_next->port && user.cell == chain_next->cell;
+ }),
+ carry->users.end());
+
+ std::unique_ptr<NetInfo> new_cout(new NetInfo());
+ new_cout->name = ctx->id(feedout->name.str(ctx) + "$COUT");
+ connect_port(ctx, new_cout.get(), feedout.get(), ctx->id("COUT"));
+
+ chain_next->cell->ports[chain_next->port].net = nullptr;
+ connect_port(ctx, new_cout.get(), chain_next->cell, chain_next->port);
+
+ IdString new_cout_name = new_cout->name;
+ ctx->nets[new_cout_name] = std::move(new_cout);
+ }
+
+ CellInfo *feedout_ptr = feedout.get();
+ IdString feedout_name = feedout->name;
+ ctx->cells[feedout_name] = std::move(feedout);
+
+ IdString new_cin_name = new_cin->name;
+ ctx->nets[new_cin_name] = std::move(new_cin);
+
+ return feedout_ptr;
+ }
+
+ // Split a carry chain into multiple legal chains
+ std::vector<CellChain> split_carry_chain(CellChain &carryc)
+ {
+ bool start_of_chain = true;
+ std::vector<CellChain> chains;
+ const int max_length = (ctx->chip_info->width - 4) * 4 - 2;
+ auto curr_cell = carryc.cells.begin();
+ while (curr_cell != carryc.cells.end()) {
+ CellInfo *cell = *curr_cell;
+ if (start_of_chain) {
+ chains.emplace_back();
+ start_of_chain = false;
+ if (cell->ports.at(ctx->id("CIN")).net) {
+ // CIN is not constant and not part of a chain. Must feed in from fabric
+ PortRef inport;
+ inport.cell = cell;
+ inport.port = ctx->id("CIN");
+ CellInfo *feedin = make_carry_feed_in(cell->ports.at(ctx->id("CIN")).net, inport);
+ chains.back().cells.push_back(feedin);
+ }
+ }
+ chains.back().cells.push_back(cell);
+ bool split_chain = int(chains.back().cells.size()) > max_length;
+ if (split_chain) {
+ CellInfo *passout = make_carry_feed_out(cell->ports.at(ctx->id("COUT")).net);
+ chains.back().cells.back() = passout;
+ start_of_chain = true;
+ } else {
+ NetInfo *carry_net = cell->ports.at(ctx->id("COUT")).net;
+ bool at_end = (curr_cell == carryc.cells.end() - 1);
+ if (carry_net != nullptr && (carry_net->users.size() > 1 || at_end)) {
+ boost::optional<PortRef> nextport;
+ if (!at_end) {
+ auto next_cell = *(curr_cell + 1);
+ PortRef nextpr;
+ nextpr.cell = next_cell;
+ nextpr.port = ctx->id("CIN");
+ nextport = nextpr;
+ }
+ CellInfo *passout = make_carry_feed_out(cell->ports.at(ctx->id("COUT")).net, nextport);
+ chains.back().cells.push_back(passout);
+ }
+ ++curr_cell;
+ }
+ }
+ return chains;
+ }
+
+ // Pack carries and set up appropriate relative constraints
+ void pack_carries()
+ {
+ log_info("Packing carries...\n");
+ // Find all chains (including single carry cells)
+ auto carry_chains = find_chains(
+ ctx, [](const Context *ctx, const CellInfo *cell) { return is_carry(ctx, cell); },
+ [](const Context *ctx, const CellInfo *cell) {
+ return net_driven_by(ctx, cell->ports.at(ctx->id("CIN")).net, is_carry, ctx->id("COUT"));
+ },
+ [](const Context *ctx, const CellInfo *cell) {
+ return net_only_drives(ctx, cell->ports.at(ctx->id("COUT")).net, is_carry, ctx->id("CIN"), false);
+ },
+ 1);
+ std::vector<CellChain> all_chains;
+
+ // Chain splitting
+ for (auto &base_chain : carry_chains) {
+ if (ctx->verbose) {
+ log_info("Found carry chain: \n");
+ for (auto entry : base_chain.cells)
+ log_info(" %s\n", entry->name.c_str(ctx));
+ log_info("\n");
+ }
+ std::vector<CellChain> split_chains = split_carry_chain(base_chain);
+ for (auto &chain : split_chains) {
+ all_chains.push_back(chain);
+ }
+ }
+
+ std::vector<std::vector<CellInfo *>> packed_chains;
+
+ // Chain packing
+ std::vector<std::tuple<CellInfo *, CellInfo *, int>> ff_packing;
+ for (auto &chain : all_chains) {
+ int cell_count = 0;
+ std::vector<CellInfo *> tile_ffs;
+ std::vector<CellInfo *> packed_chain;
+ for (auto &cell : chain.cells) {
+ if (cell_count % 4 == 0)
+ tile_ffs.clear();
+ std::unique_ptr<CellInfo> slice =
+ create_ecp5_cell(ctx, ctx->id("TRELLIS_SLICE"), cell->name.str(ctx) + "$CCU2_SLICE");
+
+ ccu2c_to_slice(ctx, cell, slice.get());
+
+ CellInfo *ff0 = nullptr;
+ NetInfo *f0net = slice->ports.at(ctx->id("F0")).net;
+ if (f0net != nullptr) {
+ ff0 = net_only_drives(ctx, f0net, is_ff, ctx->id("DI"), false);
+ if (ff0 != nullptr && can_add_ff_to_tile(tile_ffs, ff0)) {
+ ff_packing.push_back(std::make_tuple(ff0, slice.get(), 0));
+ tile_ffs.push_back(ff0);
+ packed_cells.insert(ff0->name);
+ }
+ }
+
+ CellInfo *ff1 = nullptr;
+ NetInfo *f1net = slice->ports.at(ctx->id("F1")).net;
+ if (f1net != nullptr) {
+ ff1 = net_only_drives(ctx, f1net, is_ff, ctx->id("DI"), false);
+ if (ff1 != nullptr && (ff0 == nullptr || can_pack_ffs(ff0, ff1)) &&
+ can_add_ff_to_tile(tile_ffs, ff1)) {
+ ff_packing.push_back(std::make_tuple(ff1, slice.get(), 1));
+ tile_ffs.push_back(ff1);
+ packed_cells.insert(ff1->name);
+ }
+ }
+ packed_chain.push_back(slice.get());
+ new_cells.push_back(std::move(slice));
+ packed_cells.insert(cell->name);
+ cell_count++;
+ }
+ packed_chains.push_back(packed_chain);
+ }
+
+ for (auto ff : ff_packing)
+ ff_to_slice(ctx, std::get<0>(ff), std::get<1>(ff), std::get<2>(ff), true);
+
+ // Relative chain placement
+ for (auto &chain : packed_chains) {
+ chain.at(0)->constr_abs_z = true;
+ chain.at(0)->constr_z = 0;
+ for (int i = 1; i < int(chain.size()); i++) {
+ chain.at(i)->constr_x = (i / 4);
+ chain.at(i)->constr_y = 0;
+ chain.at(i)->constr_z = i % 4;
+ chain.at(i)->constr_abs_z = true;
+ chain.at(i)->constr_parent = chain.at(0);
+ chain.at(0)->constr_children.push_back(chain.at(i));
+ }
+ }
+
+ flush_cells();
+ }
+
+ // Pack distributed RAM
+ void pack_dram()
+ {
+ for (auto cell : sorted(ctx->cells)) {
+ CellInfo *ci = cell.second;
+ if (is_dpram(ctx, ci)) {
+
+ // Create RAMW slice
+ std::unique_ptr<CellInfo> ramw_slice =
+ create_ecp5_cell(ctx, ctx->id("TRELLIS_SLICE"), ci->name.str(ctx) + "$RAMW_SLICE");
+ dram_to_ramw(ctx, ci, ramw_slice.get());
+
+ // Create actual RAM slices
+ std::unique_ptr<CellInfo> ram0_slice =
+ create_ecp5_cell(ctx, ctx->id("TRELLIS_SLICE"), ci->name.str(ctx) + "$DPRAM0_SLICE");
+ dram_to_ram_slice(ctx, ci, ram0_slice.get(), ramw_slice.get(), 0);
+
+ std::unique_ptr<CellInfo> ram1_slice =
+ create_ecp5_cell(ctx, ctx->id("TRELLIS_SLICE"), ci->name.str(ctx) + "$DPRAM1_SLICE");
+ dram_to_ram_slice(ctx, ci, ram1_slice.get(), ramw_slice.get(), 1);
+
+ // Disconnect ports of original cell after packing
+ disconnect_port(ctx, ci, id_WCK);
+ disconnect_port(ctx, ci, id_WRE);
+
+ disconnect_port(ctx, ci, ctx->id("RAD[0]"));
+ disconnect_port(ctx, ci, ctx->id("RAD[1]"));
+ disconnect_port(ctx, ci, ctx->id("RAD[2]"));
+ disconnect_port(ctx, ci, ctx->id("RAD[3]"));
+
+ // Attempt to pack FFs into RAM slices
+ std::vector<std::tuple<CellInfo *, CellInfo *, int>> ff_packing;
+ std::vector<CellInfo *> tile_ffs;
+ for (auto slice : {ram0_slice.get(), ram1_slice.get()}) {
+ CellInfo *ff0 = nullptr;
+ NetInfo *f0net = slice->ports.at(ctx->id("F0")).net;
+ if (f0net != nullptr) {
+ ff0 = net_only_drives(ctx, f0net, is_ff, ctx->id("DI"), false);
+ if (ff0 != nullptr && can_add_ff_to_tile(tile_ffs, ff0)) {
+ if (can_pack_ff_dram(slice, ff0)) {
+ ff_packing.push_back(std::make_tuple(ff0, slice, 0));
+ tile_ffs.push_back(ff0);
+ packed_cells.insert(ff0->name);
+ }
+ }
+ }
+
+ CellInfo *ff1 = nullptr;
+ NetInfo *f1net = slice->ports.at(ctx->id("F1")).net;
+ if (f1net != nullptr) {
+ ff1 = net_only_drives(ctx, f1net, is_ff, ctx->id("DI"), false);
+ if (ff1 != nullptr && (ff0 == nullptr || can_pack_ffs(ff0, ff1)) &&
+ can_add_ff_to_tile(tile_ffs, ff1)) {
+ if (can_pack_ff_dram(slice, ff1)) {
+ ff_packing.push_back(std::make_tuple(ff1, slice, 1));
+ tile_ffs.push_back(ff1);
+ packed_cells.insert(ff1->name);
+ }
+ }
+ }
+ }
+
+ for (auto ff : ff_packing)
+ ff_to_slice(ctx, std::get<0>(ff), std::get<1>(ff), std::get<2>(ff), true);
+
+ // Setup placement constraints
+ ram0_slice->constr_abs_z = true;
+ ram0_slice->constr_z = 0;
+
+ ram1_slice->constr_parent = ram0_slice.get();
+ ram1_slice->constr_abs_z = true;
+ ram1_slice->constr_x = 0;
+ ram1_slice->constr_y = 0;
+ ram1_slice->constr_z = 1;
+ ram0_slice->constr_children.push_back(ram1_slice.get());
+
+ ramw_slice->constr_parent = ram0_slice.get();
+ ramw_slice->constr_abs_z = true;
+ ramw_slice->constr_x = 0;
+ ramw_slice->constr_y = 0;
+ ramw_slice->constr_z = 2;
+ ram0_slice->constr_children.push_back(ramw_slice.get());
+
+ new_cells.push_back(std::move(ram0_slice));
+ new_cells.push_back(std::move(ram1_slice));
+ new_cells.push_back(std::move(ramw_slice));
+ packed_cells.insert(ci->name);
+ }
+ }
+ flush_cells();
+ }
+
// Pack LUTs that have been paired together
void pack_lut_pairs()
{
@@ -394,14 +754,12 @@ class Ecp5Packer
flush_cells();
}
- void set_lut_input_constant(CellInfo *cell, IdString input, bool value)
+ int make_init_with_const_input(int init, int input, bool value)
{
- int index = std::string("ABCD").find(input.str(ctx));
- int init = int_or_default(cell->params, ctx->id("INIT"));
int new_init = 0;
for (int i = 0; i < 16; i++) {
- if (((i >> index) & 0x1) != value) {
- int other_i = (i & (~(1 << index))) | (value << index);
+ if (((i >> input) & 0x1) != value) {
+ int other_i = (i & (~(1 << input))) | (value << input);
if ((init >> other_i) & 0x1)
new_init |= (1 << i);
} else {
@@ -409,10 +767,41 @@ class Ecp5Packer
new_init |= (1 << i);
}
}
+ return new_init;
+ }
+
+ void set_lut_input_constant(CellInfo *cell, IdString input, bool value)
+ {
+ int index = std::string("ABCD").find(input.str(ctx));
+ int init = int_or_default(cell->params, ctx->id("INIT"));
+ int new_init = make_init_with_const_input(init, index, value);
cell->params[ctx->id("INIT")] = std::to_string(new_init);
cell->ports.at(input).net = nullptr;
}
+ void set_ccu2c_input_constant(CellInfo *cell, IdString input, bool value)
+ {
+ std::string input_str = input.str(ctx);
+ int lut = std::stoi(input_str.substr(1));
+ int index = std::string("ABCD").find(input_str[0]);
+ int init = int_or_default(cell->params, ctx->id("INIT" + std::to_string(lut)));
+ int new_init = make_init_with_const_input(init, index, value);
+ cell->params[ctx->id("INIT" + std::to_string(lut))] = std::to_string(new_init);
+ cell->ports.at(input).net = nullptr;
+ }
+
+ bool is_ccu2c_port_high(CellInfo *cell, IdString input)
+ {
+ if (!cell->ports.count(input))
+ return true; // disconnected port is high
+ if (cell->ports.at(input).net == nullptr || cell->ports.at(input).net->name == ctx->id("$PACKER_VCC_NET"))
+ return true; // disconnected or tied-high port
+ if (cell->ports.at(input).net->driver.cell != nullptr &&
+ cell->ports.at(input).net->driver.cell->type == ctx->id("VCC"))
+ return true; // pre-pack high
+ return false;
+ }
+
// Merge a net into a constant net
void set_net_constant(const Context *ctx, NetInfo *orig, NetInfo *constnet, bool constval)
{
@@ -427,10 +816,68 @@ class Ecp5Packer
} else if (is_ff(ctx, uc) && user.port == ctx->id("CE")) {
uc->params[ctx->id("CEMUX")] = constval ? "1" : "0";
uc->ports[user.port].net = nullptr;
+ } else if (is_carry(ctx, uc)) {
+ if (constval &&
+ (user.port == id_A0 || user.port == id_A1 || user.port == id_B0 || user.port == id_B1 ||
+ user.port == id_C0 || user.port == id_C1 || user.port == id_D0 || user.port == id_D1)) {
+ // Input tied high, nothing special to do (bitstream gen will auto-enable tie-high)
+ uc->ports[user.port].net = nullptr;
+ } else if (!constval) {
+ if (user.port == id_A0 || user.port == id_A1 || user.port == id_B0 || user.port == id_B1) {
+ // These inputs can be switched to tie-high without consequence
+ set_ccu2c_input_constant(uc, user.port, constval);
+ } else if (user.port == id_C0 && is_ccu2c_port_high(uc, id_D0)) {
+ // Partner must be tied high
+ set_ccu2c_input_constant(uc, user.port, constval);
+ } else if (user.port == id_D0 && is_ccu2c_port_high(uc, id_C0)) {
+ // Partner must be tied high
+ set_ccu2c_input_constant(uc, user.port, constval);
+ } else if (user.port == id_C1 && is_ccu2c_port_high(uc, id_D1)) {
+ // Partner must be tied high
+ set_ccu2c_input_constant(uc, user.port, constval);
+ } else if (user.port == id_D1 && is_ccu2c_port_high(uc, id_C1)) {
+ // Partner must be tied high
+ set_ccu2c_input_constant(uc, user.port, constval);
+ } else {
+ // Not allowed to change to a tie-high
+ uc->ports[user.port].net = constnet;
+ constnet->users.push_back(user);
+ }
+ } else {
+ uc->ports[user.port].net = constnet;
+ constnet->users.push_back(user);
+ }
} else if (is_ff(ctx, uc) && user.port == ctx->id("LSR") &&
((!constval && str_or_default(uc->params, ctx->id("LSRMUX"), "LSR") == "LSR") ||
(constval && str_or_default(uc->params, ctx->id("LSRMUX"), "LSR") == "INV"))) {
uc->ports[user.port].net = nullptr;
+ } else if (uc->type == id_DP16KD) {
+ if (user.port == id_CLKA || user.port == id_CLKB || user.port == id_RSTA || user.port == id_RSTB ||
+ user.port == id_WEA || user.port == id_WEB || user.port == id_CEA || user.port == id_CEB ||
+ user.port == id_OCEA || user.port == id_OCEB || user.port == id_CSA0 || user.port == id_CSA1 ||
+ user.port == id_CSA2 || user.port == id_CSB0 || user.port == id_CSB1 || user.port == id_CSB2) {
+ // Connect to CIB CLK, LSR or CE. Default state is 1
+ uc->params[ctx->id(user.port.str(ctx) + "MUX")] = constval ? user.port.str(ctx) : "INV";
+ } else {
+ // Connected to CIB ABCD. Default state is bitstream configurable
+ uc->params[ctx->id(user.port.str(ctx) + "MUX")] = constval ? "1" : "0";
+ }
+ uc->ports[user.port].net = nullptr;
+ } else if (uc->type == id_ALU54B || uc->type == id_MULT18X18D) {
+ if (user.port.str(ctx).substr(0, 3) == "CLK" || user.port.str(ctx).substr(0, 2) == "CE" ||
+ user.port.str(ctx).substr(0, 3) == "RST" || user.port.str(ctx).substr(0, 3) == "SRO" ||
+ user.port.str(ctx).substr(0, 3) == "SRI" || user.port.str(ctx).substr(0, 2) == "RO" ||
+ user.port.str(ctx).substr(0, 2) == "MA" || user.port.str(ctx).substr(0, 2) == "MB" ||
+ user.port.str(ctx).substr(0, 3) == "CFB" || user.port.str(ctx).substr(0, 3) == "CIN" ||
+ user.port.str(ctx).substr(0, 6) == "SOURCE" || user.port.str(ctx).substr(0, 6) == "SIGNED" ||
+ user.port.str(ctx).substr(0, 2) == "OP") {
+ uc->ports[user.port].net = constnet;
+ constnet->users.push_back(user);
+ } else {
+ // Connected to CIB ABCD. Default state is bitstream configurable
+ uc->params[ctx->id(user.port.str(ctx) + "MUX")] = constval ? "1" : "0";
+ uc->ports[user.port].net = nullptr;
+ }
} else {
uc->ports[user.port].net = constnet;
constnet->users.push_back(user);
@@ -496,17 +943,113 @@ class Ecp5Packer
}
}
+ void autocreate_empty_port(CellInfo *cell, IdString port)
+ {
+ if (!cell->ports.count(port)) {
+ cell->ports[port].name = port;
+ cell->ports[port].net = nullptr;
+ cell->ports[port].type = PORT_IN;
+ }
+ }
+
+ // Pack EBR
+ void pack_ebr()
+ {
+ // Autoincrement WID (starting from 3 seems to match vendor behaviour?)
+ int wid = 3;
+ for (auto cell : sorted(ctx->cells)) {
+ CellInfo *ci = cell.second;
+ if (ci->type == id_DP16KD) {
+ // Add ports, even if disconnected, to ensure correct tie-offs
+ for (int i = 0; i < 14; i++) {
+ autocreate_empty_port(ci, ctx->id("ADA" + std::to_string(i)));
+ autocreate_empty_port(ci, ctx->id("ADB" + std::to_string(i)));
+ }
+ for (int i = 0; i < 18; i++) {
+ autocreate_empty_port(ci, ctx->id("DIA" + std::to_string(i)));
+ autocreate_empty_port(ci, ctx->id("DIB" + std::to_string(i)));
+ }
+ for (int i = 0; i < 3; i++) {
+ autocreate_empty_port(ci, ctx->id("CSA" + std::to_string(i)));
+ autocreate_empty_port(ci, ctx->id("CSB" + std::to_string(i)));
+ }
+ for (int i = 0; i < 3; i++) {
+ autocreate_empty_port(ci, ctx->id("CSA" + std::to_string(i)));
+ autocreate_empty_port(ci, ctx->id("CSB" + std::to_string(i)));
+ }
+
+ autocreate_empty_port(ci, id_CLKA);
+ autocreate_empty_port(ci, id_CEA);
+ autocreate_empty_port(ci, id_OCEA);
+ autocreate_empty_port(ci, id_WEA);
+ autocreate_empty_port(ci, id_RSTA);
+
+ autocreate_empty_port(ci, id_CLKB);
+ autocreate_empty_port(ci, id_CEB);
+ autocreate_empty_port(ci, id_OCEB);
+ autocreate_empty_port(ci, id_WEB);
+ autocreate_empty_port(ci, id_RSTB);
+
+ ci->attrs[ctx->id("WID")] = std::to_string(wid++);
+ }
+ }
+ }
+
+ // Pack DSPs
+ void pack_dsps()
+ {
+ for (auto cell : sorted(ctx->cells)) {
+ CellInfo *ci = cell.second;
+ if (ci->type == id_MULT18X18D) {
+ // Add ports, even if disconnected, to ensure correct tie-offs
+ for (auto sig : {"CLK", "CE", "RST"})
+ for (int i = 0; i < 4; i++)
+ autocreate_empty_port(ci, ctx->id(sig + std::to_string(i)));
+ for (auto sig : {"SIGNED", "SOURCE"})
+ for (auto c : {"A", "B"})
+ autocreate_empty_port(ci, ctx->id(sig + std::string(c)));
+ for (auto port : {"A", "B", "C"})
+ for (int i = 0; i < 18; i++)
+ autocreate_empty_port(ci, ctx->id(port + std::to_string(i)));
+ for (auto port : {"SRIA", "SRIB"})
+ for (int i = 0; i < 18; i++)
+ autocreate_empty_port(ci, ctx->id(port + std::to_string(i)));
+ } else if (ci->type == id_ALU54B) {
+ for (auto sig : {"CLK", "CE", "RST"})
+ for (int i = 0; i < 4; i++)
+ autocreate_empty_port(ci, ctx->id(sig + std::to_string(i)));
+ autocreate_empty_port(ci, id_SIGNEDIA);
+ autocreate_empty_port(ci, id_SIGNEDIB);
+ autocreate_empty_port(ci, id_SIGNEDCIN);
+ for (auto port : {"A", "B", "MA", "MB"})
+ for (int i = 0; i < 36; i++)
+ autocreate_empty_port(ci, ctx->id(port + std::to_string(i)));
+ for (auto port : {"C", "CFB", "CIN"})
+ for (int i = 0; i < 54; i++)
+ autocreate_empty_port(ci, ctx->id(port + std::to_string(i)));
+ for (int i = 0; i < 11; i++)
+ autocreate_empty_port(ci, ctx->id("OP" + std::to_string(i)));
+ }
+ }
+ }
+
public:
void pack()
{
pack_io();
+ pack_ebr();
+ pack_dsps();
pack_constants();
+ pack_dram();
+ pack_carries();
find_lutff_pairs();
pack_lut5s();
pair_luts();
pack_lut_pairs();
pack_remaining_luts();
pack_remaining_ffs();
+ promote_ecp5_globals(ctx);
+ ctx->check();
}
private:
@@ -549,6 +1092,13 @@ void Arch::assignArchInfo()
for (auto cell : sorted(cells)) {
CellInfo *ci = cell.second;
if (ci->type == id_TRELLIS_SLICE) {
+
+ ci->sliceInfo.using_dff = false;
+ if (ci->ports.count(id_Q0) && ci->ports[id_Q0].net != nullptr)
+ ci->sliceInfo.using_dff = true;
+ if (ci->ports.count(id_Q1) && ci->ports[id_Q1].net != nullptr)
+ ci->sliceInfo.using_dff = true;
+
if (ci->ports.count(id_CLK) && ci->ports[id_CLK].net != nullptr)
ci->sliceInfo.clk_sig = ci->ports[id_CLK].net->name;
else
diff --git a/ecp5/trellis_import.py b/ecp5/trellis_import.py
index de8e9958..9a26b605 100755
--- a/ecp5/trellis_import.py
+++ b/ecp5/trellis_import.py
@@ -128,7 +128,12 @@ def process_loc_globals(chip):
for x in range(0, max_col+1):
quad = chip.global_data.get_quadrant(y, x)
tapdrv = chip.global_data.get_tap_driver(y, x)
- global_data[x, y] = (quadrants.index(quad), int(tapdrv.dir), tapdrv.col)
+ if tapdrv.col == x:
+ spinedrv = chip.global_data.get_spine_driver(quad, x)
+ spine = (spinedrv.second, spinedrv.first)
+ else:
+ spine = (-1, -1)
+ global_data[x, y] = (quadrants.index(quad), int(tapdrv.dir), tapdrv.col, spine)
def get_wire_type(name):
if "H00" in name or "V00" in name:
@@ -282,6 +287,8 @@ def write_database(dev_name, chip, ddrg, endianness):
bba.u16(global_data[x, y][2], "tap_col")
bba.u8(global_data[x, y][1], "tap_dir")
bba.u8(global_data[x, y][0], "quad")
+ bba.u16(global_data[x, y][3][1], "spine_row")
+ bba.u16(global_data[x, y][3][0], "spine_col")
for package, pkgdata in sorted(packages.items()):
bba.l("package_data_%s" % package, "PackagePinPOD")
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-06 01:39:30 +0000