diff options
Diffstat (limited to 'ecp5/pack.cc')
| -rw-r--r-- | ecp5/pack.cc | 566 |
1 files changed, 558 insertions, 8 deletions
diff --git a/ecp5/pack.cc b/ecp5/pack.cc index a2077204..73e15609 100644 --- a/ecp5/pack.cc +++ b/ecp5/pack.cc @@ -18,13 +18,15 @@ */ #include <algorithm> +#include <boost/optional.hpp> #include <iterator> #include <unordered_set> #include "cells.h" +#include "chain_utils.h" #include "design_utils.h" +#include "globals.h" #include "log.h" #include "util.h" - NEXTPNR_NAMESPACE_BEGIN static bool is_nextpnr_iob(Context *ctx, CellInfo *cell) @@ -106,6 +108,41 @@ class Ecp5Packer return true; } + // Return whether or not an FF can be added to a tile (pairing checks must also be done using the fn above) + bool can_add_ff_to_tile(const std::vector<CellInfo *> &tile_ffs, CellInfo *ff0) + { + for (const auto &existing : tile_ffs) { + if (net_or_nullptr(existing, ctx->id("CLK")) != net_or_nullptr(ff0, ctx->id("CLK"))) + return false; + if (net_or_nullptr(existing, ctx->id("LSR")) != net_or_nullptr(ff0, ctx->id("LSR"))) + return false; + if (str_or_default(existing->params, ctx->id("CLKMUX"), "CLK") != + str_or_default(ff0->params, ctx->id("CLKMUX"), "CLK")) + return false; + if (str_or_default(existing->params, ctx->id("LSRMUX"), "LSR") != + str_or_default(ff0->params, ctx->id("LSRMUX"), "LSR")) + return false; + if (str_or_default(existing->params, ctx->id("SRMODE"), "LSR_OVER_CE") != + str_or_default(ff0->params, ctx->id("SRMODE"), "LSR_OVER_CE")) + return false; + } + return true; + } + + // Return true if a FF can be added to a DPRAM slice + bool can_pack_ff_dram(CellInfo *dpram, CellInfo *ff) + { + std::string wckmux = str_or_default(dpram->params, ctx->id("WCKMUX"), "WCK"); + std::string clkmux = str_or_default(ff->params, ctx->id("CLKMUX"), "CLK"); + if (wckmux != clkmux && !(wckmux == "WCK" && clkmux == "CLK")) + return false; + std::string wremux = str_or_default(dpram->params, ctx->id("WREMUX"), "WRE"); + std::string lsrmux = str_or_default(ff->params, ctx->id("LSRMUX"), "LSR"); + if (wremux != lsrmux && !(wremux == "WRE" && lsrmux == "LSR")) + return false; + return true; + } + // Return true if two LUTs can be paired considering FF compatibility bool can_pack_lutff(IdString lut0, IdString lut1) { @@ -230,11 +267,17 @@ class Ecp5Packer } } } else { - log_error("TRELLIS_IO required on all top level IOs...\n"); + // Create a TRELLIS_IO buffer + std::unique_ptr<CellInfo> tr_cell = + create_ecp5_cell(ctx, ctx->id("TRELLIS_IO"), ci->name.str(ctx) + "$tr_io"); + nxio_to_tr(ctx, ci, tr_cell.get(), new_cells, packed_cells); + new_cells.push_back(std::move(tr_cell)); + trio = new_cells.back().get(); } packed_cells.insert(ci->name); - std::copy(ci->attrs.begin(), ci->attrs.end(), std::inserter(trio->attrs, trio->attrs.begin())); + for (const auto &attr : ci->attrs) + trio->attrs[attr.first] = attr.second; auto loc_attr = trio->attrs.find(ctx->id("LOC")); if (loc_attr != trio->attrs.end()) { @@ -312,6 +355,323 @@ class Ecp5Packer flush_cells(); } + // Create a feed in to the carry chain + CellInfo *make_carry_feed_in(NetInfo *carry, PortRef chain_in) + { + std::unique_ptr<CellInfo> feedin = create_ecp5_cell(ctx, ctx->id("CCU2C")); + + feedin->params[ctx->id("INIT0")] = "10"; // LUT4 = 0; LUT2 = A + feedin->params[ctx->id("INIT1")] = "65535"; + feedin->params[ctx->id("INJECT1_0")] = "NO"; + feedin->params[ctx->id("INJECT1_1")] = "YES"; + + carry->users.erase(std::remove_if(carry->users.begin(), carry->users.end(), + [chain_in](const PortRef &user) { + return user.port == chain_in.port && user.cell == chain_in.cell; + }), + carry->users.end()); + connect_port(ctx, carry, feedin.get(), id_A0); + + std::unique_ptr<NetInfo> new_carry(new NetInfo()); + new_carry->name = ctx->id(feedin->name.str(ctx) + "$COUT"); + connect_port(ctx, new_carry.get(), feedin.get(), ctx->id("COUT")); + chain_in.cell->ports[chain_in.port].net = nullptr; + connect_port(ctx, new_carry.get(), chain_in.cell, chain_in.port); + + CellInfo *feedin_ptr = feedin.get(); + IdString feedin_name = feedin->name; + ctx->cells[feedin_name] = std::move(feedin); + IdString new_carry_name = new_carry->name; + ctx->nets[new_carry_name] = std::move(new_carry); + return feedin_ptr; + } + + // Create a feed out and loop through from the carry chain + CellInfo *make_carry_feed_out(NetInfo *carry, boost::optional<PortRef> chain_next = boost::optional<PortRef>()) + { + std::unique_ptr<CellInfo> feedout = create_ecp5_cell(ctx, ctx->id("CCU2C")); + feedout->params[ctx->id("INIT0")] = "0"; + feedout->params[ctx->id("INIT1")] = "10"; // LUT4 = 0; LUT2 = A + feedout->params[ctx->id("INJECT1_0")] = "NO"; + feedout->params[ctx->id("INJECT1_1")] = "NO"; + + PortRef carry_drv = carry->driver; + carry->driver.cell = nullptr; + connect_port(ctx, carry, feedout.get(), ctx->id("S0")); + + std::unique_ptr<NetInfo> new_cin(new NetInfo()); + new_cin->name = ctx->id(feedout->name.str(ctx) + "$CIN"); + new_cin->driver = carry_drv; + carry_drv.cell->ports.at(carry_drv.port).net = new_cin.get(); + connect_port(ctx, new_cin.get(), feedout.get(), ctx->id("CIN")); + + if (chain_next) { + // Loop back into LUT4_1 for feedthrough + connect_port(ctx, carry, feedout.get(), id_A1); + + carry->users.erase(std::remove_if(carry->users.begin(), carry->users.end(), + [chain_next](const PortRef &user) { + return user.port == chain_next->port && user.cell == chain_next->cell; + }), + carry->users.end()); + + std::unique_ptr<NetInfo> new_cout(new NetInfo()); + new_cout->name = ctx->id(feedout->name.str(ctx) + "$COUT"); + connect_port(ctx, new_cout.get(), feedout.get(), ctx->id("COUT")); + + chain_next->cell->ports[chain_next->port].net = nullptr; + connect_port(ctx, new_cout.get(), chain_next->cell, chain_next->port); + + IdString new_cout_name = new_cout->name; + ctx->nets[new_cout_name] = std::move(new_cout); + } + + CellInfo *feedout_ptr = feedout.get(); + IdString feedout_name = feedout->name; + ctx->cells[feedout_name] = std::move(feedout); + + IdString new_cin_name = new_cin->name; + ctx->nets[new_cin_name] = std::move(new_cin); + + return feedout_ptr; + } + + // Split a carry chain into multiple legal chains + std::vector<CellChain> split_carry_chain(CellChain &carryc) + { + bool start_of_chain = true; + std::vector<CellChain> chains; + const int max_length = (ctx->chip_info->width - 4) * 4 - 2; + auto curr_cell = carryc.cells.begin(); + while (curr_cell != carryc.cells.end()) { + CellInfo *cell = *curr_cell; + if (start_of_chain) { + chains.emplace_back(); + start_of_chain = false; + if (cell->ports.at(ctx->id("CIN")).net) { + // CIN is not constant and not part of a chain. Must feed in from fabric + PortRef inport; + inport.cell = cell; + inport.port = ctx->id("CIN"); + CellInfo *feedin = make_carry_feed_in(cell->ports.at(ctx->id("CIN")).net, inport); + chains.back().cells.push_back(feedin); + } + } + chains.back().cells.push_back(cell); + bool split_chain = int(chains.back().cells.size()) > max_length; + if (split_chain) { + CellInfo *passout = make_carry_feed_out(cell->ports.at(ctx->id("COUT")).net); + chains.back().cells.back() = passout; + start_of_chain = true; + } else { + NetInfo *carry_net = cell->ports.at(ctx->id("COUT")).net; + bool at_end = (curr_cell == carryc.cells.end() - 1); + if (carry_net != nullptr && (carry_net->users.size() > 1 || at_end)) { + boost::optional<PortRef> nextport; + if (!at_end) { + auto next_cell = *(curr_cell + 1); + PortRef nextpr; + nextpr.cell = next_cell; + nextpr.port = ctx->id("CIN"); + nextport = nextpr; + } + CellInfo *passout = make_carry_feed_out(cell->ports.at(ctx->id("COUT")).net, nextport); + chains.back().cells.push_back(passout); + } + ++curr_cell; + } + } + return chains; + } + + // Pack carries and set up appropriate relative constraints + void pack_carries() + { + log_info("Packing carries...\n"); + // Find all chains (including single carry cells) + auto carry_chains = find_chains( + ctx, [](const Context *ctx, const CellInfo *cell) { return is_carry(ctx, cell); }, + [](const Context *ctx, const CellInfo *cell) { + return net_driven_by(ctx, cell->ports.at(ctx->id("CIN")).net, is_carry, ctx->id("COUT")); + }, + [](const Context *ctx, const CellInfo *cell) { + return net_only_drives(ctx, cell->ports.at(ctx->id("COUT")).net, is_carry, ctx->id("CIN"), false); + }, + 1); + std::vector<CellChain> all_chains; + + // Chain splitting + for (auto &base_chain : carry_chains) { + if (ctx->verbose) { + log_info("Found carry chain: \n"); + for (auto entry : base_chain.cells) + log_info(" %s\n", entry->name.c_str(ctx)); + log_info("\n"); + } + std::vector<CellChain> split_chains = split_carry_chain(base_chain); + for (auto &chain : split_chains) { + all_chains.push_back(chain); + } + } + + std::vector<std::vector<CellInfo *>> packed_chains; + + // Chain packing + std::vector<std::tuple<CellInfo *, CellInfo *, int>> ff_packing; + for (auto &chain : all_chains) { + int cell_count = 0; + std::vector<CellInfo *> tile_ffs; + std::vector<CellInfo *> packed_chain; + for (auto &cell : chain.cells) { + if (cell_count % 4 == 0) + tile_ffs.clear(); + std::unique_ptr<CellInfo> slice = + create_ecp5_cell(ctx, ctx->id("TRELLIS_SLICE"), cell->name.str(ctx) + "$CCU2_SLICE"); + + ccu2c_to_slice(ctx, cell, slice.get()); + + CellInfo *ff0 = nullptr; + NetInfo *f0net = slice->ports.at(ctx->id("F0")).net; + if (f0net != nullptr) { + ff0 = net_only_drives(ctx, f0net, is_ff, ctx->id("DI"), false); + if (ff0 != nullptr && can_add_ff_to_tile(tile_ffs, ff0)) { + ff_packing.push_back(std::make_tuple(ff0, slice.get(), 0)); + tile_ffs.push_back(ff0); + packed_cells.insert(ff0->name); + } + } + + CellInfo *ff1 = nullptr; + NetInfo *f1net = slice->ports.at(ctx->id("F1")).net; + if (f1net != nullptr) { + ff1 = net_only_drives(ctx, f1net, is_ff, ctx->id("DI"), false); + if (ff1 != nullptr && (ff0 == nullptr || can_pack_ffs(ff0, ff1)) && + can_add_ff_to_tile(tile_ffs, ff1)) { + ff_packing.push_back(std::make_tuple(ff1, slice.get(), 1)); + tile_ffs.push_back(ff1); + packed_cells.insert(ff1->name); + } + } + packed_chain.push_back(slice.get()); + new_cells.push_back(std::move(slice)); + packed_cells.insert(cell->name); + cell_count++; + } + packed_chains.push_back(packed_chain); + } + + for (auto ff : ff_packing) + ff_to_slice(ctx, std::get<0>(ff), std::get<1>(ff), std::get<2>(ff), true); + + // Relative chain placement + for (auto &chain : packed_chains) { + chain.at(0)->constr_abs_z = true; + chain.at(0)->constr_z = 0; + for (int i = 1; i < int(chain.size()); i++) { + chain.at(i)->constr_x = (i / 4); + chain.at(i)->constr_y = 0; + chain.at(i)->constr_z = i % 4; + chain.at(i)->constr_abs_z = true; + chain.at(i)->constr_parent = chain.at(0); + chain.at(0)->constr_children.push_back(chain.at(i)); + } + } + + flush_cells(); + } + + // Pack distributed RAM + void pack_dram() + { + for (auto cell : sorted(ctx->cells)) { + CellInfo *ci = cell.second; + if (is_dpram(ctx, ci)) { + + // Create RAMW slice + std::unique_ptr<CellInfo> ramw_slice = + create_ecp5_cell(ctx, ctx->id("TRELLIS_SLICE"), ci->name.str(ctx) + "$RAMW_SLICE"); + dram_to_ramw(ctx, ci, ramw_slice.get()); + + // Create actual RAM slices + std::unique_ptr<CellInfo> ram0_slice = + create_ecp5_cell(ctx, ctx->id("TRELLIS_SLICE"), ci->name.str(ctx) + "$DPRAM0_SLICE"); + dram_to_ram_slice(ctx, ci, ram0_slice.get(), ramw_slice.get(), 0); + + std::unique_ptr<CellInfo> ram1_slice = + create_ecp5_cell(ctx, ctx->id("TRELLIS_SLICE"), ci->name.str(ctx) + "$DPRAM1_SLICE"); + dram_to_ram_slice(ctx, ci, ram1_slice.get(), ramw_slice.get(), 1); + + // Disconnect ports of original cell after packing + disconnect_port(ctx, ci, id_WCK); + disconnect_port(ctx, ci, id_WRE); + + disconnect_port(ctx, ci, ctx->id("RAD[0]")); + disconnect_port(ctx, ci, ctx->id("RAD[1]")); + disconnect_port(ctx, ci, ctx->id("RAD[2]")); + disconnect_port(ctx, ci, ctx->id("RAD[3]")); + + // Attempt to pack FFs into RAM slices + std::vector<std::tuple<CellInfo *, CellInfo *, int>> ff_packing; + std::vector<CellInfo *> tile_ffs; + for (auto slice : {ram0_slice.get(), ram1_slice.get()}) { + CellInfo *ff0 = nullptr; + NetInfo *f0net = slice->ports.at(ctx->id("F0")).net; + if (f0net != nullptr) { + ff0 = net_only_drives(ctx, f0net, is_ff, ctx->id("DI"), false); + if (ff0 != nullptr && can_add_ff_to_tile(tile_ffs, ff0)) { + if (can_pack_ff_dram(slice, ff0)) { + ff_packing.push_back(std::make_tuple(ff0, slice, 0)); + tile_ffs.push_back(ff0); + packed_cells.insert(ff0->name); + } + } + } + + CellInfo *ff1 = nullptr; + NetInfo *f1net = slice->ports.at(ctx->id("F1")).net; + if (f1net != nullptr) { + ff1 = net_only_drives(ctx, f1net, is_ff, ctx->id("DI"), false); + if (ff1 != nullptr && (ff0 == nullptr || can_pack_ffs(ff0, ff1)) && + can_add_ff_to_tile(tile_ffs, ff1)) { + if (can_pack_ff_dram(slice, ff1)) { + ff_packing.push_back(std::make_tuple(ff1, slice, 1)); + tile_ffs.push_back(ff1); + packed_cells.insert(ff1->name); + } + } + } + } + + for (auto ff : ff_packing) + ff_to_slice(ctx, std::get<0>(ff), std::get<1>(ff), std::get<2>(ff), true); + + // Setup placement constraints + ram0_slice->constr_abs_z = true; + ram0_slice->constr_z = 0; + + ram1_slice->constr_parent = ram0_slice.get(); + ram1_slice->constr_abs_z = true; + ram1_slice->constr_x = 0; + ram1_slice->constr_y = 0; + ram1_slice->constr_z = 1; + ram0_slice->constr_children.push_back(ram1_slice.get()); + + ramw_slice->constr_parent = ram0_slice.get(); + ramw_slice->constr_abs_z = true; + ramw_slice->constr_x = 0; + ramw_slice->constr_y = 0; + ramw_slice->constr_z = 2; + ram0_slice->constr_children.push_back(ramw_slice.get()); + + new_cells.push_back(std::move(ram0_slice)); + new_cells.push_back(std::move(ram1_slice)); + new_cells.push_back(std::move(ramw_slice)); + packed_cells.insert(ci->name); + } + } + flush_cells(); + } + // Pack LUTs that have been paired together void pack_lut_pairs() { @@ -394,14 +754,12 @@ class Ecp5Packer flush_cells(); } - void set_lut_input_constant(CellInfo *cell, IdString input, bool value) + int make_init_with_const_input(int init, int input, bool value) { - int index = std::string("ABCD").find(input.str(ctx)); - int init = int_or_default(cell->params, ctx->id("INIT")); int new_init = 0; for (int i = 0; i < 16; i++) { - if (((i >> index) & 0x1) != value) { - int other_i = (i & (~(1 << index))) | (value << index); + if (((i >> input) & 0x1) != value) { + int other_i = (i & (~(1 << input))) | (value << input); if ((init >> other_i) & 0x1) new_init |= (1 << i); } else { @@ -409,10 +767,41 @@ class Ecp5Packer new_init |= (1 << i); } } + return new_init; + } + + void set_lut_input_constant(CellInfo *cell, IdString input, bool value) + { + int index = std::string("ABCD").find(input.str(ctx)); + int init = int_or_default(cell->params, ctx->id("INIT")); + int new_init = make_init_with_const_input(init, index, value); cell->params[ctx->id("INIT")] = std::to_string(new_init); cell->ports.at(input).net = nullptr; } + void set_ccu2c_input_constant(CellInfo *cell, IdString input, bool value) + { + std::string input_str = input.str(ctx); + int lut = std::stoi(input_str.substr(1)); + int index = std::string("ABCD").find(input_str[0]); + int init = int_or_default(cell->params, ctx->id("INIT" + std::to_string(lut))); + int new_init = make_init_with_const_input(init, index, value); + cell->params[ctx->id("INIT" + std::to_string(lut))] = std::to_string(new_init); + cell->ports.at(input).net = nullptr; + } + + bool is_ccu2c_port_high(CellInfo *cell, IdString input) + { + if (!cell->ports.count(input)) + return true; // disconnected port is high + if (cell->ports.at(input).net == nullptr || cell->ports.at(input).net->name == ctx->id("$PACKER_VCC_NET")) + return true; // disconnected or tied-high port + if (cell->ports.at(input).net->driver.cell != nullptr && + cell->ports.at(input).net->driver.cell->type == ctx->id("VCC")) + return true; // pre-pack high + return false; + } + // Merge a net into a constant net void set_net_constant(const Context *ctx, NetInfo *orig, NetInfo *constnet, bool constval) { @@ -427,10 +816,68 @@ class Ecp5Packer } else if (is_ff(ctx, uc) && user.port == ctx->id("CE")) { uc->params[ctx->id("CEMUX")] = constval ? "1" : "0"; uc->ports[user.port].net = nullptr; + } else if (is_carry(ctx, uc)) { + if (constval && + (user.port == id_A0 || user.port == id_A1 || user.port == id_B0 || user.port == id_B1 || + user.port == id_C0 || user.port == id_C1 || user.port == id_D0 || user.port == id_D1)) { + // Input tied high, nothing special to do (bitstream gen will auto-enable tie-high) + uc->ports[user.port].net = nullptr; + } else if (!constval) { + if (user.port == id_A0 || user.port == id_A1 || user.port == id_B0 || user.port == id_B1) { + // These inputs can be switched to tie-high without consequence + set_ccu2c_input_constant(uc, user.port, constval); + } else if (user.port == id_C0 && is_ccu2c_port_high(uc, id_D0)) { + // Partner must be tied high + set_ccu2c_input_constant(uc, user.port, constval); + } else if (user.port == id_D0 && is_ccu2c_port_high(uc, id_C0)) { + // Partner must be tied high + set_ccu2c_input_constant(uc, user.port, constval); + } else if (user.port == id_C1 && is_ccu2c_port_high(uc, id_D1)) { + // Partner must be tied high + set_ccu2c_input_constant(uc, user.port, constval); + } else if (user.port == id_D1 && is_ccu2c_port_high(uc, id_C1)) { + // Partner must be tied high + set_ccu2c_input_constant(uc, user.port, constval); + } else { + // Not allowed to change to a tie-high + uc->ports[user.port].net = constnet; + constnet->users.push_back(user); + } + } else { + uc->ports[user.port].net = constnet; + constnet->users.push_back(user); + } } else if (is_ff(ctx, uc) && user.port == ctx->id("LSR") && ((!constval && str_or_default(uc->params, ctx->id("LSRMUX"), "LSR") == "LSR") || (constval && str_or_default(uc->params, ctx->id("LSRMUX"), "LSR") == "INV"))) { uc->ports[user.port].net = nullptr; + } else if (uc->type == id_DP16KD) { + if (user.port == id_CLKA || user.port == id_CLKB || user.port == id_RSTA || user.port == id_RSTB || + user.port == id_WEA || user.port == id_WEB || user.port == id_CEA || user.port == id_CEB || + user.port == id_OCEA || user.port == id_OCEB || user.port == id_CSA0 || user.port == id_CSA1 || + user.port == id_CSA2 || user.port == id_CSB0 || user.port == id_CSB1 || user.port == id_CSB2) { + // Connect to CIB CLK, LSR or CE. Default state is 1 + uc->params[ctx->id(user.port.str(ctx) + "MUX")] = constval ? user.port.str(ctx) : "INV"; + } else { + // Connected to CIB ABCD. Default state is bitstream configurable + uc->params[ctx->id(user.port.str(ctx) + "MUX")] = constval ? "1" : "0"; + } + uc->ports[user.port].net = nullptr; + } else if (uc->type == id_ALU54B || uc->type == id_MULT18X18D) { + if (user.port.str(ctx).substr(0, 3) == "CLK" || user.port.str(ctx).substr(0, 2) == "CE" || + user.port.str(ctx).substr(0, 3) == "RST" || user.port.str(ctx).substr(0, 3) == "SRO" || + user.port.str(ctx).substr(0, 3) == "SRI" || user.port.str(ctx).substr(0, 2) == "RO" || + user.port.str(ctx).substr(0, 2) == "MA" || user.port.str(ctx).substr(0, 2) == "MB" || + user.port.str(ctx).substr(0, 3) == "CFB" || user.port.str(ctx).substr(0, 3) == "CIN" || + user.port.str(ctx).substr(0, 6) == "SOURCE" || user.port.str(ctx).substr(0, 6) == "SIGNED" || + user.port.str(ctx).substr(0, 2) == "OP") { + uc->ports[user.port].net = constnet; + constnet->users.push_back(user); + } else { + // Connected to CIB ABCD. Default state is bitstream configurable + uc->params[ctx->id(user.port.str(ctx) + "MUX")] = constval ? "1" : "0"; + uc->ports[user.port].net = nullptr; + } } else { uc->ports[user.port].net = constnet; constnet->users.push_back(user); @@ -496,17 +943,113 @@ class Ecp5Packer } } + void autocreate_empty_port(CellInfo *cell, IdString port) + { + if (!cell->ports.count(port)) { + cell->ports[port].name = port; + cell->ports[port].net = nullptr; + cell->ports[port].type = PORT_IN; + } + } + + // Pack EBR + void pack_ebr() + { + // Autoincrement WID (starting from 3 seems to match vendor behaviour?) + int wid = 3; + for (auto cell : sorted(ctx->cells)) { + CellInfo *ci = cell.second; + if (ci->type == id_DP16KD) { + // Add ports, even if disconnected, to ensure correct tie-offs + for (int i = 0; i < 14; i++) { + autocreate_empty_port(ci, ctx->id("ADA" + std::to_string(i))); + autocreate_empty_port(ci, ctx->id("ADB" + std::to_string(i))); + } + for (int i = 0; i < 18; i++) { + autocreate_empty_port(ci, ctx->id("DIA" + std::to_string(i))); + autocreate_empty_port(ci, ctx->id("DIB" + std::to_string(i))); + } + for (int i = 0; i < 3; i++) { + autocreate_empty_port(ci, ctx->id("CSA" + std::to_string(i))); + autocreate_empty_port(ci, ctx->id("CSB" + std::to_string(i))); + } + for (int i = 0; i < 3; i++) { + autocreate_empty_port(ci, ctx->id("CSA" + std::to_string(i))); + autocreate_empty_port(ci, ctx->id("CSB" + std::to_string(i))); + } + + autocreate_empty_port(ci, id_CLKA); + autocreate_empty_port(ci, id_CEA); + autocreate_empty_port(ci, id_OCEA); + autocreate_empty_port(ci, id_WEA); + autocreate_empty_port(ci, id_RSTA); + + autocreate_empty_port(ci, id_CLKB); + autocreate_empty_port(ci, id_CEB); + autocreate_empty_port(ci, id_OCEB); + autocreate_empty_port(ci, id_WEB); + autocreate_empty_port(ci, id_RSTB); + + ci->attrs[ctx->id("WID")] = std::to_string(wid++); + } + } + } + + // Pack DSPs + void pack_dsps() + { + for (auto cell : sorted(ctx->cells)) { + CellInfo *ci = cell.second; + if (ci->type == id_MULT18X18D) { + // Add ports, even if disconnected, to ensure correct tie-offs + for (auto sig : {"CLK", "CE", "RST"}) + for (int i = 0; i < 4; i++) + autocreate_empty_port(ci, ctx->id(sig + std::to_string(i))); + for (auto sig : {"SIGNED", "SOURCE"}) + for (auto c : {"A", "B"}) + autocreate_empty_port(ci, ctx->id(sig + std::string(c))); + for (auto port : {"A", "B", "C"}) + for (int i = 0; i < 18; i++) + autocreate_empty_port(ci, ctx->id(port + std::to_string(i))); + for (auto port : {"SRIA", "SRIB"}) + for (int i = 0; i < 18; i++) + autocreate_empty_port(ci, ctx->id(port + std::to_string(i))); + } else if (ci->type == id_ALU54B) { + for (auto sig : {"CLK", "CE", "RST"}) + for (int i = 0; i < 4; i++) + autocreate_empty_port(ci, ctx->id(sig + std::to_string(i))); + autocreate_empty_port(ci, id_SIGNEDIA); + autocreate_empty_port(ci, id_SIGNEDIB); + autocreate_empty_port(ci, id_SIGNEDCIN); + for (auto port : {"A", "B", "MA", "MB"}) + for (int i = 0; i < 36; i++) + autocreate_empty_port(ci, ctx->id(port + std::to_string(i))); + for (auto port : {"C", "CFB", "CIN"}) + for (int i = 0; i < 54; i++) + autocreate_empty_port(ci, ctx->id(port + std::to_string(i))); + for (int i = 0; i < 11; i++) + autocreate_empty_port(ci, ctx->id("OP" + std::to_string(i))); + } + } + } + public: void pack() { pack_io(); + pack_ebr(); + pack_dsps(); pack_constants(); + pack_dram(); + pack_carries(); find_lutff_pairs(); pack_lut5s(); pair_luts(); pack_lut_pairs(); pack_remaining_luts(); pack_remaining_ffs(); + promote_ecp5_globals(ctx); + ctx->check(); } private: @@ -549,6 +1092,13 @@ void Arch::assignArchInfo() for (auto cell : sorted(cells)) { CellInfo *ci = cell.second; if (ci->type == id_TRELLIS_SLICE) { + + ci->sliceInfo.using_dff = false; + if (ci->ports.count(id_Q0) && ci->ports[id_Q0].net != nullptr) + ci->sliceInfo.using_dff = true; + if (ci->ports.count(id_Q1) && ci->ports[id_Q1].net != nullptr) + ci->sliceInfo.using_dff = true; + if (ci->ports.count(id_CLK) && ci->ports[id_CLK].net != nullptr) ci->sliceInfo.clk_sig = ci->ports[id_CLK].net->name; else |