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* trans-chap9.adb: destroy types in PSL expressions. For #2157Tristan Gingold2022-08-041-3/+31
* vhdl-prints: improve outputTristan Gingold2022-08-032-2/+23
* psl-build.adb: disable incorrect optimization. Fix #2157Tristan Gingold2022-08-032-2/+5
* trans-chap3: translate subtype indication of access subtype. Fix #2152Tristan Gingold2022-07-301-3/+14
* psl-nodes: add commentsTristan Gingold2022-07-301-0/+2
* psl-rewrites.adb: fix inclusive before. Fix #2153Tristan Gingold2022-07-291-1/+3
* vhdl-sem_stmts: set stop_flag on call to stop and severity failure.Tristan Gingold2022-07-291-22/+56
* vhdl-nodes: add Get/Set_Stop_Flag. For #2150Tristan Gingold2022-07-294-116/+164
* netlists-memories: allow X in memories. Fix #2146Tristan Gingold2022-07-291-2/+4
* netlists-disp_verilog(disp_const_log): fix output. Fix #2149Tristan Gingold2022-07-281-2/+2
* synth-disp_vhdl: fix out conversion. Fix #2145Tristan Gingold2022-07-281-21/+29
* vhdl: check read for attribute parameter and aggregates. Fix #2148Tristan Gingold2022-07-282-3/+20
* vhdl-sem_names: add implicit function call for array attributes. Fix #2147Tristan Gingold2022-07-281-40/+8
* options.adb: -Werror=X enables warning X.Tristan Gingold2022-07-281-0/+1
* synth-vhdl_expr: add support for branch quantitiesTristan Gingold2022-07-282-0/+2
* simul-vhdl_simul: add scalar terminal tableTristan Gingold2022-07-281-0/+16
* simul-vhdl_debug: add info terminalTristan Gingold2022-07-281-20/+69
* vhdl-sem_names: allow element attribute on element attribute. Fix #2141Tristan Gingold2022-07-284-17/+34
* elab-vhdl_expr: fix handling of multi-dim arrays. Fix #2144Tristan Gingold2022-07-271-9/+17
* synth-disp_vhdl: improve output for unsigned. Fix #2139Tristan Gingold2022-07-271-2/+17
* elab-vhdl_expr: fix incorrect type of multi-dim array indexing during elabTristan Gingold2022-07-271-0/+9
* synthesis.adb: cleanup after expand. For #2142Tristan Gingold2022-07-271-0/+2
* netlists-disp_vhdl: adjust output for #2140Tristan Gingold2022-07-271-2/+8
* netlists-expands: do not try to clean input of dyn_extract. Fix #2142Tristan Gingold2022-07-271-5/+1
* netlist-disp_vhdl: add a separator between instances and signals.Tristan Gingold2022-07-261-1/+1
* vhdl-parse: set reference_terminal flagTristan Gingold2022-07-261-0/+1
* vhdl-canon: handle conditional variable assignment. Fix #2138Tristan Gingold2022-07-251-1/+16
* simul: gather terminalsTristan Gingold2022-07-254-3/+74
* synth/elab-vhdl_values: add Value_TerminalTristan Gingold2022-07-256-4/+38
* vhdl-nodes: add Get/Set_Reference_Terminal_FlagTristan Gingold2022-07-254-204/+247
* synth-environment: fix memory crash. Fix #2139Tristan Gingold2022-07-251-2/+8
* dyn_tables,tables: add Reserve. For #2139Tristan Gingold2022-07-254-5/+28
* src/simul: rewrite of ghdl/simul based on synthTristan Gingold2022-07-247-0/+3759
* synth: add hook for dot attributeTristan Gingold2022-07-243-7/+17
* vhdl: handle element attribute in declarations. Fix #2136Tristan Gingold2022-07-212-12/+23
* elab-vhdl_decls: elaborate dot attributeTristan Gingold2022-07-213-4/+14
* vhdl-nodes: renaming.Tristan Gingold2022-07-2121-128/+130
* elab-vhdl_decls: elaborate implicit signalsTristan Gingold2022-07-211-2/+23
* Makefile.in: allow build of ghdl_mcode with sundials enabledTristan Gingold2022-07-211-0/+25
* synth-vhdl_expr: add hook for quantitiesTristan Gingold2022-07-202-11/+23
* elab-vhdl_debug: handle signals in packagesTristan Gingold2022-07-201-2/+8
* grt: add analog_solver (work in progress)Tristan Gingold2022-07-204-9/+197
* grt: add real now variable.Tristan Gingold2022-07-204-0/+19
* ghdlsimul: simplify elaboration circuiteryTristan Gingold2022-07-201-13/+0
* elab-vhdl_context: add iterator for top-level packagesTristan Gingold2022-07-202-0/+36
* configure: add --with-sundials (preliminary work)Tristan Gingold2022-07-202-0/+44
* elab-vhdl_debug: disp fp64 valuesTristan Gingold2022-07-204-2/+10
* vhdl-sem_specs: allow protected body in scope of an attribute. Fix #2134Tristan Gingold2022-07-161-0/+2
* vhdl: preliminary work to elaborat quantitiesTristan Gingold2022-07-167-2/+26
* elab-vhdl_values: add Create_Value_QuantityTristan Gingold2022-07-166-2/+41
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