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| author | Tristan Gingold <tgingold@free.fr> | 2022-07-16 08:31:03 +0200 | 
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-07-16 08:31:03 +0200 | 
| commit | ae7667c05858b9d7f6c1637a06497dfa138f635e (patch) | |
| tree | f44915b0e2147190f5123056febe0ff429fbe347 /src | |
| parent | 37d38f613b065b59b6d13aabaad3295861504296 (diff) | |
| download | ghdl-ae7667c05858b9d7f6c1637a06497dfa138f635e.tar.gz ghdl-ae7667c05858b9d7f6c1637a06497dfa138f635e.tar.bz2 ghdl-ae7667c05858b9d7f6c1637a06497dfa138f635e.zip  | |
elab-vhdl_values: add Create_Value_Quantity
Diffstat (limited to 'src')
| -rw-r--r-- | src/synth/elab-vhdl_debug.adb | 2 | ||||
| -rw-r--r-- | src/synth/elab-vhdl_values-debug.adb | 4 | ||||
| -rw-r--r-- | src/synth/elab-vhdl_values.adb | 25 | ||||
| -rw-r--r-- | src/synth/elab-vhdl_values.ads | 9 | ||||
| -rw-r--r-- | src/synth/synth-vhdl_context.adb | 2 | ||||
| -rw-r--r-- | src/synth/synth-vhdl_insts.adb | 1 | 
6 files changed, 41 insertions, 2 deletions
diff --git a/src/synth/elab-vhdl_debug.adb b/src/synth/elab-vhdl_debug.adb index 68ba51bf5..ea7736193 100644 --- a/src/synth/elab-vhdl_debug.adb +++ b/src/synth/elab-vhdl_debug.adb @@ -229,6 +229,8 @@ package body Elab.Vhdl_Debug is              Put_Uns32 (Uns32 (Vt.Val.S));           when Value_File =>              Put ("file"); +         when Value_Quantity => +            Put ("quantity");           when Value_Const =>              Put ("const: ");              Disp_Memtyp (Get_Memtyp (Vt), Vtype); diff --git a/src/synth/elab-vhdl_values-debug.adb b/src/synth/elab-vhdl_values-debug.adb index a7cf2f9a3..bd174f6b0 100644 --- a/src/synth/elab-vhdl_values-debug.adb +++ b/src/synth/elab-vhdl_values-debug.adb @@ -304,6 +304,10 @@ package body Elab.Vhdl_Values.Debug is              New_Line;           when Value_File =>              Put_Line ("a file"); +         when Value_Quantity => +            Put ("quantity "); +            Put_Uns32 (Uns32 (V.Val.Q)); +            New_Line;           when Value_Alias =>              Put ("an alias: ");              Debug_Typ1 (V.Typ); diff --git a/src/synth/elab-vhdl_values.adb b/src/synth/elab-vhdl_values.adb index c5485c400..12953b869 100644 --- a/src/synth/elab-vhdl_values.adb +++ b/src/synth/elab-vhdl_values.adb @@ -33,7 +33,8 @@ package body Elab.Vhdl_Values is           when Value_Net             | Value_Wire             | Value_Signal -           | Value_Dyn_Alias => +           | Value_Dyn_Alias +           | Value_Quantity =>              return False;           when Value_File =>              return True; @@ -182,6 +183,23 @@ package body Elab.Vhdl_Values is        return (Vtype, Create_Value_File (File));     end Create_Value_File; +   function Create_Value_Quantity (Q : Quantity_Index_Type) return Value_Acc +   is +      subtype Value_Type_Quantity is Value_Type (Value_Quantity); +      function Alloc is new Areapools.Alloc_On_Pool_Addr (Value_Type_Quantity); +   begin +      return To_Value_Acc (Alloc (Current_Pool, +                                  (Kind => Value_Quantity, Q => Q))); +   end Create_Value_Quantity; + +   function Create_Value_Quantity (Vtype : Type_Acc; Q : Quantity_Index_Type) +                                  return Valtyp +   is +      pragma Assert (Vtype /= null); +   begin +      return (Vtype, Create_Value_Quantity (Q)); +   end Create_Value_Quantity; +     function Create_Value_Alias       (Obj : Valtyp; Off : Value_Offsets; Typ : Type_Acc) return Valtyp     is @@ -268,6 +286,8 @@ package body Elab.Vhdl_Values is              Res := (Src.Typ, Create_Value_Wire (Src.Val.N));           when Value_File =>              Res := Create_Value_File (Src.Typ, Src.Val.File); +         when Value_Quantity => +            raise Internal_Error;           when Value_Signal =>              raise Internal_Error;           when Value_Const => @@ -491,7 +511,8 @@ package body Elab.Vhdl_Values is              end;           when Value_Const =>              return Get_Memtyp ((V.Typ, V.Val.C_Val)); -         when Value_File => +         when Value_File +           | Value_Quantity =>              raise Internal_Error;        end case;     end Get_Memtyp; diff --git a/src/synth/elab-vhdl_values.ads b/src/synth/elab-vhdl_values.ads index b1aad9ce1..0ffdf2381 100644 --- a/src/synth/elab-vhdl_values.ads +++ b/src/synth/elab-vhdl_values.ads @@ -48,6 +48,7 @@ package Elab.Vhdl_Values is        Value_Memory,        Value_File, +      Value_Quantity,        --  A constant.  This is a named value.  One purpose is to avoid to        --  create many times the same net for the same value. @@ -73,6 +74,9 @@ package Elab.Vhdl_Values is     type Signal_Index_Type is new Uns32;     No_Signal_Index : constant Signal_Index_Type := 0; +   type Quantity_Index_Type is new Uns32; +   No_Quantity_Index : constant Quantity_Index_Type := 0; +     type Value_Type (Kind : Value_Kind) is record        case Kind is           when Value_Net @@ -85,6 +89,8 @@ package Elab.Vhdl_Values is              Mem : Memory_Ptr;           when Value_File =>              File : File_Index; +         when Value_Quantity => +            Q : Quantity_Index_Type;           when Value_Const =>              C_Val : Value_Acc;              C_Loc : Node; @@ -148,6 +154,9 @@ package Elab.Vhdl_Values is     function Create_Value_File (Vtype : Type_Acc; File : File_Index)                                return Valtyp; +   function Create_Value_Quantity (Vtype : Type_Acc; Q : Quantity_Index_Type) +                                  return Valtyp; +     function Create_Value_Alias       (Obj : Valtyp; Off : Value_Offsets; Typ : Type_Acc) return Valtyp; diff --git a/src/synth/synth-vhdl_context.adb b/src/synth/synth-vhdl_context.adb index f9c1edb39..6e498afdf 100644 --- a/src/synth/synth-vhdl_context.adb +++ b/src/synth/synth-vhdl_context.adb @@ -448,6 +448,8 @@ package body Synth.Vhdl_Context is             | Value_Signal             | Value_Dyn_Alias =>              return False; +         when Value_Quantity => +            return False;           when Value_Wire =>              declare                 W : constant Wire_Id := Get_Value_Wire (Val); diff --git a/src/synth/synth-vhdl_insts.adb b/src/synth/synth-vhdl_insts.adb index cf7814276..92ea9def3 100644 --- a/src/synth/synth-vhdl_insts.adb +++ b/src/synth/synth-vhdl_insts.adb @@ -228,6 +228,7 @@ package body Synth.Vhdl_Insts is             | Value_Wire             | Value_Signal             | Value_File +           | Value_Quantity             | Value_Dyn_Alias =>              raise Internal_Error;        end case;  | 
