| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | synth-vhdl_insts: also handled unbounded records in hash names. | Tristan Gingold | 2022-07-02 | 1 | -0/+7 |
| * | vhdl-sem_psl: analyze strong properties | Tristan Gingold | 2022-07-02 | 1 | -1/+2 |
| * | vhdl-sem_names: avoid crash on incorrect selected name. | Tristan Gingold | 2022-07-02 | 1 | -6/+6 |
| * | vhdl-sem_decls: avoid crash on self use of a generic package. | Tristan Gingold | 2022-07-02 | 1 | -0/+10 |
| * | vhdl: avoid crash on incorrect use of attributes. | Tristan Gingold | 2022-07-02 | 5 | -14/+40 |
| * | vhdl: avoid crash on incorrect use of signatures | Tristan Gingold | 2022-07-02 | 3 | -281/+292 |
| * | vhdl-evaluation: handle more operations (thought synth). | Tristan Gingold | 2022-07-02 | 1 | -2/+1 |
| * | vhdl-sem_names: avoid duplicate error message. For #2100 | Tristan Gingold | 2022-06-28 | 1 | -1/+19 |
| * | netlists-disp_verilog: adjust, discard null signals. For #2113 | Tristan Gingold | 2022-06-28 | 1 | -1/+6 |
| * | netlists-disp_verilog: fix warning | Tristan Gingold | 2022-06-27 | 1 | -1/+2 |
| * | synth/netlists-disp_verilog: skip null input port. Fix #2113 | Tristan Gingold | 2022-06-27 | 1 | -15/+20 |
| * | synth: rework #2109 - remove null wires | Tristan Gingold | 2022-06-27 | 8 | -26/+87 |
| * | synth/netlists-disp_verilog: adjust previous patch. For #2109 | Tristan Gingold | 2022-06-27 | 1 | -1/+2 |
| * | netlists-disp_verilog: do not display ports of width 0. Fix #2109 | Tristan Gingold | 2022-06-27 | 1 | -5/+19 |
| * | Fix nested comments | sudden6 | 2022-06-26 | 1 | -41/+41 |
| * | vhdl-parse: fix crashes after error. Fix #2110 | Tristan Gingold | 2022-06-26 | 1 | -2/+6 |
| * | vhdl-parse_psl: avoid crash on error. For #2110 | Tristan Gingold | 2022-06-26 | 1 | -1/+7 |
| * | trans-chap8: adjust conditions to pass parameters. Fix #2104 | Tristan Gingold | 2022-06-22 | 1 | -2/+9 |
| * | vhdl-sem.adb: avoid a crash on conformance error. Fix #2103 | Tristan Gingold | 2022-06-21 | 1 | -2/+2 |
| * | vhdl-sem_lib: do not disable warnings for files in -c/-r | Tristan Gingold | 2022-06-19 | 1 | -1/+5 |
| * | trans-chap7: translate anonymous subtype of overflow literal. Fox #2066 | Tristan Gingold | 2022-06-19 | 1 | -2/+6 |
| * | vhdl-sem_expr: check expression index range for aggregate. Fix #2066 | Tristan Gingold | 2022-06-19 | 1 | -0/+25 |
| * | synth-vhdl_insts(synth_single_input_assoc): handle type conversion. | Tristan Gingold | 2022-06-16 | 2 | -4/+13 |
| * | vhdl-sem.adb(are_trees_equal): handle simple aggregate. | Tristan Gingold | 2022-06-16 | 1 | -14/+12 |
| * | vhdl/translate: handle inertial association in recursive instantiation | Tristan Gingold | 2022-06-16 | 2 | -2/+16 |
| * | vhdl-sem_names: handle element and subtype attributes for type conv. | Tristan Gingold | 2022-06-16 | 1 | -22/+26 |
| * | vhdl-sem_expr: do not attribute element or subtype attributes as expr. | Tristan Gingold | 2022-06-16 | 1 | -0/+2 |
| * | vhdl: handle 'element in 'range. Fix #2071 | Tristan Gingold | 2022-06-15 | 2 | -23/+104 |
| * | Add comments | Tristan Gingold | 2022-06-15 | 2 | -1/+2 |
| * | netlists-rename: handle handle signal instances. Fix #2093 | Tristan Gingold | 2022-06-15 | 3 | -2/+28 |
| * | src/synth: add netlists.rename to rename identifiers. Fix #2054 | Tristan Gingold | 2022-06-14 | 4 | -2/+132 |
| * | netlists-disp_verilog: do not display blackboxes. Fix #2092 | Tristan Gingold | 2022-06-13 | 1 | -0/+5 |
| * | netlists-disp_verilog: Use blocking assignments in non-clocked blocks | Anton Blanchard | 2022-06-13 | 1 | -10/+10 |
| * | vhdl: add a parent field to protected_type_declaration. Fix #2091 | Tristan Gingold | 2022-06-12 | 3 | -265/+271 |
| * | synth-vhdl_insts: handle actual conversion function. Fix #2090 | Tristan Gingold | 2022-06-12 | 1 | -12/+38 |
| * | elab-vhdl_insts: eval inertial expressions to get the type. Fix #2089 | Tristan Gingold | 2022-06-12 | 2 | -7/+18 |
| * | vhdl-nodes: add Inertial_Flag for association_element_by_expression | Tristan Gingold | 2022-06-12 | 5 | -302/+347 |
| * | elab-vhdl_types(Synth_Array_Attribute): handle dimension parameter | Tristan Gingold | 2022-06-11 | 1 | -1/+3 |
| * | synth-environment(Merge_Dyn_Insert): disable transformation. | Tristan Gingold | 2022-06-11 | 1 | -1/+3 |
| * | netlists-memories: handle negation for In_Conjunction. Fix #2086 | Tristan Gingold | 2022-06-11 | 1 | -8/+3 |
| * | synth-vhdl_eval: add support for more operations | Tristan Gingold | 2022-06-11 | 1 | -1/+10 |
| * | vhdl: recognize ieee.math_real.sign, fix is_x recogn. | Tristan Gingold | 2022-06-11 | 7 | -18/+51 |
| * | deleted pragma messages | Guiltybyte | 2022-06-09 | 1 | -2/+0 |
| * | Only enable backtrace on linux if glibc is present | Guiltybyte | 2022-06-09 | 1 | -1/+3 |
| * | elab-vhdl_types(Elab_Declaration_Type): rework to handle 'subtype | Tristan Gingold | 2022-06-09 | 7 | -30/+64 |
| * | vhdl-annotations: avoid a crash with subtype attribute in array. | Tristan Gingold | 2022-06-09 | 3 | -5/+16 |
| * | synth-vhdl_expr.adb: use base type for indexed names. Fix #2083 | Tristan Gingold | 2022-06-08 | 1 | -1/+2 |
| * | synth-vhdl_expr: add an hook for signal attributes | Tristan Gingold | 2022-06-08 | 2 | -0/+11 |
| * | synth-vhdl_eval: handle more operations | Tristan Gingold | 2022-06-07 | 1 | -8/+17 |
| * | vhdl-sem: adjust condition to set suspend_state on procedures | Tristan Gingold | 2022-06-07 | 3 | -15/+36 |
