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| author | Tristan Gingold <tgingold@free.fr> | 2022-06-27 20:59:16 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-06-27 20:59:16 +0200 |
| commit | dabf31c2b12633033cea5a177f0deefe28c05c9b (patch) | |
| tree | cb52936fae160ce9a819720d40307123d411dfa7 /src | |
| parent | 223ea757ec1959bfa0be149071fd5568c4c61982 (diff) | |
| download | ghdl-dabf31c2b12633033cea5a177f0deefe28c05c9b.tar.gz ghdl-dabf31c2b12633033cea5a177f0deefe28c05c9b.tar.bz2 ghdl-dabf31c2b12633033cea5a177f0deefe28c05c9b.zip | |
netlists-disp_verilog: fix warning
Diffstat (limited to 'src')
| -rw-r--r-- | src/synth/netlists-disp_verilog.adb | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/synth/netlists-disp_verilog.adb b/src/synth/netlists-disp_verilog.adb index 3097e758a..47fa0047a 100644 --- a/src/synth/netlists-disp_verilog.adb +++ b/src/synth/netlists-disp_verilog.adb @@ -246,13 +246,14 @@ package body Netlists.Disp_Verilog is -- Outputs Idx := 0; for O of Outputs (Inst) loop + Desc := Get_Output_Desc (Imod, Idx); if First then First := False; else Put_Line (","); end if; Put (" ."); - Put_Interface_Name (Get_Output_Desc (Imod, Idx).Name); + Put_Interface_Name (Desc.Name); Idx := Idx + 1; Put ("("); declare |