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| author | Tristan Gingold <tgingold@free.fr> | 2022-06-16 21:46:58 +0200 | 
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-06-16 21:46:58 +0200 | 
| commit | 70e663c7a398f5ef8bdf181d73f5a7cd39d34a6f (patch) | |
| tree | 0026b181800958417bc9bf3b73184b4be5d5994f /src | |
| parent | 9fc52765b1e9d75ffbb4700bb60df2ccf5c6fcc5 (diff) | |
| download | ghdl-70e663c7a398f5ef8bdf181d73f5a7cd39d34a6f.tar.gz ghdl-70e663c7a398f5ef8bdf181d73f5a7cd39d34a6f.tar.bz2 ghdl-70e663c7a398f5ef8bdf181d73f5a7cd39d34a6f.zip  | |
vhdl-sem.adb(are_trees_equal): handle simple aggregate.
Fix #2098
Diffstat (limited to 'src')
| -rw-r--r-- | src/vhdl/vhdl-sem.adb | 26 | 
1 files changed, 12 insertions, 14 deletions
diff --git a/src/vhdl/vhdl-sem.adb b/src/vhdl/vhdl-sem.adb index 804b11f8e..924ad9429 100644 --- a/src/vhdl/vhdl-sem.adb +++ b/src/vhdl/vhdl-sem.adb @@ -1391,20 +1391,14 @@ package body Vhdl.Sem is        --  A simple name can be replaced by an expanded name in which this        --  simple name is the selector, if and only if at both places the        --  meaning of the simple name is given by the same declaration. -      case Get_Kind (Left) is -         when Iir_Kind_Simple_Name -           | Iir_Kind_Selected_Name => -            case Get_Kind (Right) is -               when Iir_Kind_Simple_Name -                 | Iir_Kind_Selected_Name => -                  return Are_Trees_Equal (Get_Named_Entity (Left), -                                          Get_Named_Entity (Right)); -               when others => -                  return False; -            end case; -         when others => -            null; -      end case; +      if Get_Kind (Left) in Iir_Kinds_Denoting_Name then +         if Get_Kind (Right) in Iir_Kinds_Denoting_Name then +            return Are_Trees_Equal (Get_Named_Entity (Left), +                                    Get_Named_Entity (Right)); +         else +            return False; +         end if; +      end if;        --  If nodes are not of the same kind, then they are not equals!        if Get_Kind (Left) /= Get_Kind (Right) then @@ -1657,6 +1651,10 @@ package body Vhdl.Sem is                (Get_Association_Choices_Chain (Left),                 Get_Association_Choices_Chain (Right)); +         when Iir_Kind_Simple_Aggregate => +            return Are_Trees_Equal (Get_Literal_Origin (Left), +                                    Get_Literal_Origin (Right)); +           when Iir_Kind_Choice_By_None                | Iir_Kind_Choice_By_Others =>              return Are_Trees_Equal (Get_Associated_Expr (Left),  | 
