aboutsummaryrefslogtreecommitdiffstats
path: root/src
Commit message (Collapse)AuthorAgeFilesLines
* vhdl-evaluation: explicitly compute integer_exp to handle overflow.Tristan Gingold2022-07-071-2/+31
| | | | Tentatively fix crash on mingw32
* vhdl-evaluation: make overflow_literal non locally static.Tristan Gingold2022-07-072-1/+6
| | | | Fix crash in translation (tentatively)
* netlists-disp_verilog: fix output for id_abs. For #2123Tristan Gingold2022-07-061-1/+2
|
* synth-vhdl_oper: handle is_x for signed/unsigned. Fix #2129Tristan Gingold2022-07-061-1/+3
|
* Fix issue #2126, add handling of to_ux01 to synthesisMichael Nolan2022-07-051-1/+3
|
* synth-vhdl_insts: do not crash on unconnected input. Fix #2124Tristan Gingold2022-07-051-0/+4
|
* netlists-disp_verilog: handle Id_Abs. Fix #2113Tristan Gingold2022-07-041-1/+1
|
* synth-vhdl_insts: also handled unbounded records in hash names.Tristan Gingold2022-07-021-0/+7
| | | | Fix #2119
* vhdl-sem_psl: analyze strong propertiesTristan Gingold2022-07-021-1/+2
| | | | For #2116
* vhdl-sem_names: avoid crash on incorrect selected name.Tristan Gingold2022-07-021-6/+6
| | | | For #2116
* vhdl-sem_decls: avoid crash on self use of a generic package.Tristan Gingold2022-07-021-0/+10
| | | | For #2116
* vhdl: avoid crash on incorrect use of attributes.Tristan Gingold2022-07-025-14/+40
| | | | For #2116
* vhdl: avoid crash on incorrect use of signaturesTristan Gingold2022-07-023-281/+292
| | | | For #2116
* vhdl-evaluation: handle more operations (thought synth).Tristan Gingold2022-07-021-2/+1
| | | | For #2116
* vhdl-sem_names: avoid duplicate error message. For #2100Tristan Gingold2022-06-281-1/+19
|
* netlists-disp_verilog: adjust, discard null signals. For #2113Tristan Gingold2022-06-281-1/+6
|
* netlists-disp_verilog: fix warningTristan Gingold2022-06-271-1/+2
|
* synth/netlists-disp_verilog: skip null input port. Fix #2113Tristan Gingold2022-06-271-15/+20
|
* synth: rework #2109 - remove null wiresTristan Gingold2022-06-278-26/+87
|
* synth/netlists-disp_verilog: adjust previous patch. For #2109Tristan Gingold2022-06-271-1/+2
|
* netlists-disp_verilog: do not display ports of width 0. Fix #2109Tristan Gingold2022-06-271-5/+19
|
* Fix nested commentssudden62022-06-261-41/+41
|
* vhdl-parse: fix crashes after error. Fix #2110Tristan Gingold2022-06-261-2/+6
|
* vhdl-parse_psl: avoid crash on error. For #2110Tristan Gingold2022-06-261-1/+7
|
* trans-chap8: adjust conditions to pass parameters. Fix #2104Tristan Gingold2022-06-221-2/+9
|
* vhdl-sem.adb: avoid a crash on conformance error. Fix #2103Tristan Gingold2022-06-211-2/+2
|
* vhdl-sem_lib: do not disable warnings for files in -c/-rTristan Gingold2022-06-191-1/+5
|
* trans-chap7: translate anonymous subtype of overflow literal. Fox #2066Tristan Gingold2022-06-191-2/+6
|
* vhdl-sem_expr: check expression index range for aggregate. Fix #2066Tristan Gingold2022-06-191-0/+25
|
* synth-vhdl_insts(synth_single_input_assoc): handle type conversion.Tristan Gingold2022-06-162-4/+13
| | | | Fix #2099
* vhdl-sem.adb(are_trees_equal): handle simple aggregate.Tristan Gingold2022-06-161-14/+12
| | | | Fix #2098
* vhdl/translate: handle inertial association in recursive instantiationTristan Gingold2022-06-162-2/+16
| | | | Fix #2065
* vhdl-sem_names: handle element and subtype attributes for type conv.Tristan Gingold2022-06-161-22/+26
| | | | Fix #2097
* vhdl-sem_expr: do not attribute element or subtype attributes as expr.Tristan Gingold2022-06-161-0/+2
| | | | For #2097
* vhdl: handle 'element in 'range. Fix #2071Tristan Gingold2022-06-152-23/+104
|
* Add commentsTristan Gingold2022-06-152-1/+2
|
* netlists-rename: handle handle signal instances. Fix #2093Tristan Gingold2022-06-153-2/+28
|
* src/synth: add netlists.rename to rename identifiers. Fix #2054Tristan Gingold2022-06-144-2/+132
|
* netlists-disp_verilog: do not display blackboxes. Fix #2092Tristan Gingold2022-06-131-0/+5
|
* netlists-disp_verilog: Use blocking assignments in non-clocked blocksAnton Blanchard2022-06-131-10/+10
|
* vhdl: add a parent field to protected_type_declaration. Fix #2091Tristan Gingold2022-06-123-265/+271
|
* synth-vhdl_insts: handle actual conversion function. Fix #2090Tristan Gingold2022-06-121-12/+38
|
* elab-vhdl_insts: eval inertial expressions to get the type. Fix #2089Tristan Gingold2022-06-122-7/+18
|
* vhdl-nodes: add Inertial_Flag for association_element_by_expressionTristan Gingold2022-06-125-302/+347
|
* elab-vhdl_types(Synth_Array_Attribute): handle dimension parameterTristan Gingold2022-06-111-1/+3
| | | | Fix #2088
* synth-environment(Merge_Dyn_Insert): disable transformation.Tristan Gingold2022-06-111-1/+3
| | | | | | Do not transform a Dyn_Insert into a Dyn_Insert_En, to avoid spurious latch detection. For #2086
* netlists-memories: handle negation for In_Conjunction. Fix #2086Tristan Gingold2022-06-111-8/+3
|
* synth-vhdl_eval: add support for more operationsTristan Gingold2022-06-111-1/+10
|
* vhdl: recognize ieee.math_real.sign, fix is_x recogn.Tristan Gingold2022-06-117-18/+51
|
* deleted pragma messagesGuiltybyte2022-06-091-2/+0
|
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-08 10:58:34 +0000