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| author | Tristan Gingold <tgingold@free.fr> | 2022-07-04 21:11:56 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-07-04 21:12:52 +0200 |
| commit | c4f2d8305e6798a530f772887dee3592e872ac53 (patch) | |
| tree | bb0327b0f211048f985014ffadfeb5f25469b4a5 /src | |
| parent | 87caff1d542289f494816489bd01b964df5cfce0 (diff) | |
| download | ghdl-c4f2d8305e6798a530f772887dee3592e872ac53.tar.gz ghdl-c4f2d8305e6798a530f772887dee3592e872ac53.tar.bz2 ghdl-c4f2d8305e6798a530f772887dee3592e872ac53.zip | |
netlists-disp_verilog: handle Id_Abs. Fix #2113
Diffstat (limited to 'src')
| -rw-r--r-- | src/synth/netlists-disp_verilog.adb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/synth/netlists-disp_verilog.adb b/src/synth/netlists-disp_verilog.adb index cd13a6d77..7d1354403 100644 --- a/src/synth/netlists-disp_verilog.adb +++ b/src/synth/netlists-disp_verilog.adb @@ -854,7 +854,7 @@ package body Netlists.Disp_Verilog is when Id_Neg => Disp_Template (" assign \o0 = -\i0;" & NL, Inst); when Id_Abs=> - Disp_Template (" \o0 <= std_logic_vector(abs \si0);" & NL, Inst); + Disp_Template (" \o0 <= \si0 >= 0 ? \i0 : -\i0;" & NL, Inst); when Id_Extract => Disp_Template (" assign \o0 = ", Inst); Disp_Extract (Inst); |