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* elab: add default value to portsTristan Gingold2022-08-234-13/+28
* synth-vhdl_static_proc: handle std.env.finishTristan Gingold2022-08-211-1/+2
* synth: factorize code for synth_subtype_conversionTristan Gingold2022-08-219-53/+35
* simul: rework assertions execution and error handlingTristan Gingold2022-08-213-2/+9
* simul-vhdl_simul: add support for PSL directivesTristan Gingold2022-08-202-20/+22
* elab-vhdl_expr: factorize codeTristan Gingold2022-08-1910-998/+50
* simul: handle resolved signals (WIP)Tristan Gingold2022-08-192-6/+35
* elab-vhdl_objtypes: handle holes in comparisons.Tristan Gingold2022-08-161-7/+72
* netlists-memories: add a TODO commentTristan Gingold2022-08-161-0/+8
* synth/netlists: add commentsTristan Gingold2022-08-162-7/+14
* synth-vhdl_expr: optimize record with one element.Tristan Gingold2022-08-161-3/+3
* netlists-memories: renaming and add commentsTristan Gingold2022-08-161-25/+38
* elab-vhdl_values-debug: improve output of debug_valtypTristan Gingold2022-08-141-1/+3
* synth-vhdl_context: fix handling of alias in get_net. Fix #2177Tristan Gingold2022-08-141-4/+3
* vhdl: recognize log10 and sqrt from math_real. Fix #2176Tristan Gingold2022-08-141-0/+14
* synth: handle assignment to record aggregateTristan Gingold2022-08-142-31/+109
* netlists-memories: improve checks to avoid the crash of #2077Tristan Gingold2022-08-141-32/+75
* netlists-memories: fix a crash on multi-dim memories. For #2077Tristan Gingold2022-08-131-3/+6
* synth-vhdl_oper.adb: fix mul uns uns. Fix #2169Tristan Gingold2022-08-101-1/+1
* synth-vhdl_oper: remove check for positive rotation amount. Fix #2159Tristan Gingold2022-08-041-3/+1
* netlists-memories: allow X in memories. Fix #2146Tristan Gingold2022-07-291-2/+4
* netlists-disp_verilog(disp_const_log): fix output. Fix #2149Tristan Gingold2022-07-281-2/+2
* synth-disp_vhdl: fix out conversion. Fix #2145Tristan Gingold2022-07-281-21/+29
* synth-vhdl_expr: add support for branch quantitiesTristan Gingold2022-07-282-0/+2
* elab-vhdl_expr: fix handling of multi-dim arrays. Fix #2144Tristan Gingold2022-07-271-9/+17
* synth-disp_vhdl: improve output for unsigned. Fix #2139Tristan Gingold2022-07-271-2/+17
* elab-vhdl_expr: fix incorrect type of multi-dim array indexing during elabTristan Gingold2022-07-271-0/+9
* synthesis.adb: cleanup after expand. For #2142Tristan Gingold2022-07-271-0/+2
* netlists-disp_vhdl: adjust output for #2140Tristan Gingold2022-07-271-2/+8
* netlists-expands: do not try to clean input of dyn_extract. Fix #2142Tristan Gingold2022-07-271-5/+1
* netlist-disp_vhdl: add a separator between instances and signals.Tristan Gingold2022-07-261-1/+1
* simul: gather terminalsTristan Gingold2022-07-251-0/+28
* synth/elab-vhdl_values: add Value_TerminalTristan Gingold2022-07-256-4/+38
* synth-environment: fix memory crash. Fix #2139Tristan Gingold2022-07-251-2/+8
* synth: add hook for dot attributeTristan Gingold2022-07-243-7/+17
* elab-vhdl_decls: elaborate dot attributeTristan Gingold2022-07-211-0/+13
* vhdl-nodes: renaming.Tristan Gingold2022-07-212-5/+5
* elab-vhdl_decls: elaborate implicit signalsTristan Gingold2022-07-211-2/+23
* synth-vhdl_expr: add hook for quantitiesTristan Gingold2022-07-202-11/+23
* elab-vhdl_debug: handle signals in packagesTristan Gingold2022-07-201-2/+8
* grt: add real now variable.Tristan Gingold2022-07-201-0/+3
* elab-vhdl_context: add iterator for top-level packagesTristan Gingold2022-07-202-0/+36
* elab-vhdl_debug: disp fp64 valuesTristan Gingold2022-07-202-2/+3
* vhdl: preliminary work to elaborat quantitiesTristan Gingold2022-07-163-0/+17
* elab-vhdl_values: add Create_Value_QuantityTristan Gingold2022-07-166-2/+41
* netlists-inference: add (disabled) code to add a latchTristan Gingold2022-07-161-26/+103
* synth: Display dlatchTristan Gingold2022-07-143-2/+9
* netlists: add d-latchTristan Gingold2022-07-123-2/+38
* Fix access check failed from iir_kind_selected_element (#2132)Michael Nolan2022-07-121-0/+1
* synth-environment: do inference during wire finalizationTristan Gingold2022-07-111-13/+31
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