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| author | Tristan Gingold <tgingold@free.fr> | 2022-07-21 06:45:24 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-07-21 06:45:24 +0200 |
| commit | 341a8698ccb6b795d46b9570bac06e240c7664de (patch) | |
| tree | f818881d50e3da9fe055cbf3a6ce4c2472e16aaf /src/synth | |
| parent | f440e1b0289a1f969b9190a11831e384b911db0e (diff) | |
| download | ghdl-341a8698ccb6b795d46b9570bac06e240c7664de.tar.gz ghdl-341a8698ccb6b795d46b9570bac06e240c7664de.tar.bz2 ghdl-341a8698ccb6b795d46b9570bac06e240c7664de.zip | |
vhdl-nodes: renaming.
Node Iir_Kind_Signal_Attribute_Declaration is now
Iir_Kind_Attribute_Implicit_Declaration
Will also handle quantities.
Diffstat (limited to 'src/synth')
| -rw-r--r-- | src/synth/elab-vhdl_decls.adb | 6 | ||||
| -rw-r--r-- | src/synth/synth-vhdl_decls.adb | 4 |
2 files changed, 5 insertions, 5 deletions
diff --git a/src/synth/elab-vhdl_decls.adb b/src/synth/elab-vhdl_decls.adb index 12b3675bd..ffa0ee0a7 100644 --- a/src/synth/elab-vhdl_decls.adb +++ b/src/synth/elab-vhdl_decls.adb @@ -302,11 +302,11 @@ package body Elab.Vhdl_Decls is null; when Iir_Kind_Configuration_Specification => null; - when Iir_Kind_Signal_Attribute_Declaration => + when Iir_Kind_Attribute_Implicit_Declaration => declare El : Node; begin - El := Get_Signal_Attribute_Chain (Decl); + El := Get_Attribute_Implicit_Chain (Decl); while El /= Null_Node loop Elab_Declaration (Syn_Inst, El, Force_Init, Last_Type); El := Get_Attr_Chain (El); @@ -393,7 +393,7 @@ package body Elab.Vhdl_Decls is when Iir_Kind_Psl_Default_Clock => -- Ignored; directly used by PSL directives. null; - when Iir_Kind_Signal_Attribute_Declaration => + when Iir_Kind_Attribute_Implicit_Declaration => -- Not supported by synthesis. null; when others => diff --git a/src/synth/synth-vhdl_decls.adb b/src/synth/synth-vhdl_decls.adb index 56d7ab9e0..dfbedff91 100644 --- a/src/synth/synth-vhdl_decls.adb +++ b/src/synth/synth-vhdl_decls.adb @@ -625,7 +625,7 @@ package body Synth.Vhdl_Decls is null; when Iir_Kind_Configuration_Specification => null; - when Iir_Kind_Signal_Attribute_Declaration => + when Iir_Kind_Attribute_Implicit_Declaration => -- Not supported by synthesis. null; when others => @@ -765,7 +765,7 @@ package body Synth.Vhdl_Decls is when Iir_Kind_Psl_Default_Clock => -- Ignored; directly used by PSL directives. null; - when Iir_Kind_Signal_Attribute_Declaration => + when Iir_Kind_Attribute_Implicit_Declaration => -- Not supported by synthesis. null; when Iir_Kind_Package_Instantiation_Declaration => |