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| author | Tristan Gingold <tgingold@free.fr> | 2022-07-16 08:31:51 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-07-16 08:31:51 +0200 |
| commit | 7c8ed1216609d69cd6a092620d7aa1334e432fd9 (patch) | |
| tree | 82ea5a780ef0d85183008401b45bb8ed881c3fb0 /src/synth | |
| parent | ae7667c05858b9d7f6c1637a06497dfa138f635e (diff) | |
| download | ghdl-7c8ed1216609d69cd6a092620d7aa1334e432fd9.tar.gz ghdl-7c8ed1216609d69cd6a092620d7aa1334e432fd9.tar.bz2 ghdl-7c8ed1216609d69cd6a092620d7aa1334e432fd9.zip | |
vhdl: preliminary work to elaborat quantities
Diffstat (limited to 'src/synth')
| -rw-r--r-- | src/synth/elab-vhdl_decls.adb | 13 | ||||
| -rw-r--r-- | src/synth/elab-vhdl_insts.adb | 2 | ||||
| -rw-r--r-- | src/synth/elab-vhdl_stmts.adb | 2 |
3 files changed, 17 insertions, 0 deletions
diff --git a/src/synth/elab-vhdl_decls.adb b/src/synth/elab-vhdl_decls.adb index caaac05c4..821d99a99 100644 --- a/src/synth/elab-vhdl_decls.adb +++ b/src/synth/elab-vhdl_decls.adb @@ -160,6 +160,17 @@ package body Elab.Vhdl_Decls is Create_Object (Syn_Inst, Decl, Res); end Elab_File_Declaration; + procedure Elab_Free_Quantity_Declaration (Syn_Inst : Synth_Instance_Acc; + Decl : Node) + is + Obj_Typ : Type_Acc; + Res : Valtyp; + begin + Obj_Typ := Elab_Declaration_Type (Syn_Inst, Decl); + Res := Create_Value_Quantity (Obj_Typ, No_Quantity_Index); + Create_Object (Syn_Inst, Decl, Res); + end Elab_Free_Quantity_Declaration; + procedure Elab_Attribute_Specification (Syn_Inst : Synth_Instance_Acc; Spec : Node) is @@ -285,6 +296,8 @@ package body Elab.Vhdl_Decls is when Iir_Kind_Signal_Attribute_Declaration => -- Not supported by synthesis. null; + when Iir_Kind_Free_Quantity_Declaration => + Elab_Free_Quantity_Declaration (Syn_Inst, Decl); when Iir_Kind_Suspend_State_Declaration => declare Val : Valtyp; diff --git a/src/synth/elab-vhdl_insts.adb b/src/synth/elab-vhdl_insts.adb index a86c94eb1..b5c4a7bc9 100644 --- a/src/synth/elab-vhdl_insts.adb +++ b/src/synth/elab-vhdl_insts.adb @@ -472,6 +472,8 @@ package body Elab.Vhdl_Insts is | Iir_Kind_Concurrent_Conditional_Signal_Assignment | Iir_Kind_Concurrent_Selected_Signal_Assignment | Iir_Kind_Concurrent_Procedure_Call_Statement + | Iir_Kind_Concurrent_Break_Statement + | Iir_Kind_Simple_Simultaneous_Statement | Iir_Kinds_Process_Statement => null; when Iir_Kind_If_Generate_Statement => diff --git a/src/synth/elab-vhdl_stmts.adb b/src/synth/elab-vhdl_stmts.adb index 0deb80b5a..ce2648db0 100644 --- a/src/synth/elab-vhdl_stmts.adb +++ b/src/synth/elab-vhdl_stmts.adb @@ -185,6 +185,8 @@ package body Elab.Vhdl_Stmts is | Iir_Kind_Concurrent_Conditional_Signal_Assignment | Iir_Kind_Concurrent_Assertion_Statement | Iir_Kind_Concurrent_Procedure_Call_Statement + | Iir_Kind_Concurrent_Break_Statement + | Iir_Kind_Simple_Simultaneous_Statement | Iir_Kind_Psl_Default_Clock | Iir_Kind_Psl_Restrict_Directive | Iir_Kind_Psl_Assume_Directive |