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* synth-vhdl_eval: handle std_logic_misc reduce functionsTristan Gingold2022-10-191-0/+27
* synth-vhdl_oper: handle xor/nand/nor/xnor reduce from std_logic_miscTristan Gingold2022-10-191-16/+34
* synth-vhdl_oper: handle and_reduce. Fix #2224Tristan Gingold2022-10-191-1/+10
* synth: extract elab-vhdl_utils from synth-vhdl_stmts.Tristan Gingold2022-10-183-142/+241
* synth: handle record conversionTristan Gingold2022-10-141-0/+3
* synth-vhdl_expr: support alias in indexed namesTristan Gingold2022-10-141-1/+2
* synth: avoid extra conversion during alias elaborationTristan Gingold2022-10-141-6/+4
* synth: handle alias of access objects.Tristan Gingold2022-10-131-1/+1
* simul: handle last_event and last_activeTristan Gingold2022-10-132-0/+16
* elab-vhd_expr: handle more cases in exec_type_of_objectTristan Gingold2022-10-131-1/+4
* synth-vhdl_stmts(synth_verification_unit): always set instance_pool.Tristan Gingold2022-10-131-1/+3
* synth: fix crashes on scalar attribute with anonymous subtype.Tristan Gingold2022-10-101-2/+2
* simul: signal attributes in actualsTristan Gingold2022-10-061-2/+4
* simul: complete concurrent procedure callsTristan Gingold2022-10-062-2/+5
* simul: improve debugger (display of signals value)Tristan Gingold2022-10-063-11/+48
* elab-vhdl_objtypes(unshare): handle slice_type. Fix #2205Tristan Gingold2022-10-041-2/+4
* synth: avoid crash on invalid hdl in psl. Fix #2204Tristan Gingold2022-10-033-17/+46
* synth: improve error recoveryTristan Gingold2022-10-021-0/+3
* synth: detect division by 0, handle universal real/integer divisionTristan Gingold2022-10-021-3/+23
* synth-vhdl_stmts: handle passive process. Fix ghdl/ghdl-yosys-plugin#174Tristan Gingold2022-10-021-18/+204
* synth: avoid a crash on literal overflowTristan Gingold2022-10-011-1/+10
* synth: avoid on crash on overflow in rangesTristan Gingold2022-10-011-0/+8
* synth: improve handling of individual generic associationsTristan Gingold2022-10-011-17/+22
* simul: finalize declarations of procedure callsTristan Gingold2022-10-011-0/+2
* synth: handle read for floatsTristan Gingold2022-09-301-0/+12
* synth: handle float-float conversionsTristan Gingold2022-09-301-3/+14
* synth: factorize codeTristan Gingold2022-09-301-8/+1
* simul: handle quiet attributeTristan Gingold2022-09-292-5/+16
* synth: handle guard signal in debuggerTristan Gingold2022-09-281-0/+1
* simul: handle last_value attributeTristan Gingold2022-09-282-0/+8
* synth: handle guard signal in expressionsTristan Gingold2022-09-282-0/+2
* synth: handle null-range loopsTristan Gingold2022-09-284-17/+37
* synth: handle names in record aggregate targetsTristan Gingold2022-09-281-0/+12
* synth: handle array target aggregateTristan Gingold2022-09-271-2/+6
* synth: handle error on variable default valueTristan Gingold2022-09-271-0/+5
* synth-vhdl_eval: handle nor, nandTristan Gingold2022-09-261-0/+21
* synth: handle attributes in configurationsTristan Gingold2022-09-262-1/+12
* synth: improve error checks (type conversion, string literals)Tristan Gingold2022-09-253-33/+37
* synth: rework error procedure, always pass the instanceTristan Gingold2022-09-2514-251/+401
* synth-vhdl_eval: handle vhdl-87 array array concatenationTristan Gingold2022-09-251-2/+31
* synth-vhdl_stmts: fix missing newline in default assertion messagesTristan Gingold2022-09-251-3/+3
* synth: handle default expression for IN variables in assocsTristan Gingold2022-09-251-4/+10
* synth: handle selected names in targetsTristan Gingold2022-09-251-1/+2
* synth-vhdl_eval: handle null-null in array concatenationsTristan Gingold2022-09-251-0/+6
* simul: gather disconnection specifications, create guard signalTristan Gingold2022-09-251-3/+3
* synth: ignore groups and group templatesTristan Gingold2022-09-252-0/+12
* synth: handle attribute namesTristan Gingold2022-09-251-13/+16
* synth: handle individual subprogram associations for expressionsTristan Gingold2022-09-251-55/+61
* synth: rework association conversionsTristan Gingold2022-09-252-28/+64
* synth-vhdl_stmts: rework for subprogram associations (WIP)Tristan Gingold2022-09-251-57/+36
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